L64118 LSI Logic Corporation, L64118 Datasheet - Page 10
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L64118
Manufacturer Part Number
L64118
Description
Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
Manufacturer
LSI Logic Corporation
Datasheet
1.L64118.pdf
(68 pages)
- Current page: 10 of 68
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Transport Demultiplexer Block
10
1. Big-Endian means that the address of a multiple-byte data type is the address of its most
significant byte.
The L64118’s TR4101 MIPS CPU is part of LSI Logic’s CoreWare
technology. The chip integrates the complete CPU subsystem, including:
The L64118’s embedded 32-bit MIPS CPU runs at 54 MHz. This clock
rate permits a peak processing rate of 54 MIPS. The chip’s internal CPU
core is implemented in 32-bit architecture, but it can execute both 16-bit
and 32-bit instructions. The L64118 has a 16-bit data interface to
external SDRAM, and a 32-bit data interface to the external system bus
(EBus). The CPU operates in Big Endian
Since most transport processing and filtering is implemented in
hardware, much of the CPU’s processing power can be devoted to
system processing. The chip includes address decoding logic for directly
interfacing to external memory (FLASH, SDRAM) without requiring
external glue logic.
The interface between the CPU subsystem and the rest of the L64118 is
implemented by the C2P unit. The C2P module translates 32-bit data
accesses by the CPU to 8- and 16-bit data accesses on the Peripheral
Bus, which connects all other blocks. The PBus is synchronous to the
27 MHz system clock.
The transport demultiplexer block processes the transport stream data
coming from the channel interface. The input of the L64118 transport
block interfaces to the channel decoder; the output interfaces to the
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
CPU (TR4101)
Cache memory for instruction (2 x 4 Kbyte) and data (4 Kbyte) cache
Basic BIU and Cache Controller (BBCC)
Timers (including watchdog timer)
Interrupt Controller
Debugger Building Module (DBX)
Multiply/Divide Unit (MDU)
ICE port (full-duplex, serial receive and transmit port)
CPU-to-Peripheral bus (C2P)
1
mode.
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