L64118 LSI Logic Corporation, L64118 Datasheet - Page 34

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

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SBD[15:0]
SCASn
SDCLK
SDQMH
SDQML
SRASn
SWEn
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
SDRAM Data Bus
This data bus is driven by the SDRAM during a read
operation, and driven by the L64118 during a write
operation. It is 3-stated after reset and when there are no
memory accesses.
Column Address Strobe
This signal is the active LOW column address strobe. It
is used in conjunction with the SRASn and SWEn outputs
to form the SDRAM command.
SDRAM Clock
This is the master SDRAM clock. All output signals are
referenced to the rising edge of SDCLK. The
programmable SDRAM timing parameters are expressed
in SDCLK periods.
High Byte Mask
This active HIGH signal is the high byte data mask, which
controls the high byte input/output buffer of the external
SDRAM. When asserted, it disables (masks) the high
data byte of the SDRAM data bus.
GPIO6
SDQMH can serve as a general-purpose I/O signal
(GPIO6) by setting bit [0] in the General-Purpose Mode
register.
Low Byte Mask
This active HIGH signal is the low byte data mask, which
controls the low byte input/output buffer of the external
SDRAM. When asserted, it disables (masks) the low data
byte of the SDRAM data bus.
Row Address Strobe
This signal is the active LOW row address strobe. SRASn
is used in conjunction with the SCASn and SWEn outputs
to form the SDRAM command.
Write Enable
This signal is the active LOW write enable strobe. SWEn
is used in conjunction with the SRASn and SCASn
outputs to form the SDRAM command.
Bidirectional
Bidirectional
Output
Output
Output
Output
Output
Output