LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 97

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

7.9
7.10
SMSC LPC47M172
nWRITE
PD<0:7>
INTR
SIGNAL
EPP 1.7 Write
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or
Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during the
EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is
inactive high.
Write Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
EPP 1.7 Read
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip
inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle can complete when nWAIT is inactive high.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
9.
EPP
The host sets PDIR bit in the control register to a logic “0”. This asserts nWRITE.
The host initiates an I/O write cycle to the selected EPP register.
The chip places address or data on PData bus.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and
the WRITE signal is valid.
If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts
nWAIT or a time-out occurs.
The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the
internal data bus for the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
The host sets PDIR bit in the control register to a logic “1”. This deasserts nWRITE and tri-states the
PData bus.
The host initiates an I/O read cycle to the selected EPP register.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the
nWRITE signal is valid.
If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts
nWAIT or a time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination
phase of the cycle.
The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
nWrite
Address/Data
Interrupt
EPP NAME
TYPE
I/O
Table 7.2 - EPP Pin Descriptions
O
I
DATASHEET
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
Page 97
EPP DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Datasheet