LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 48
LPC47M172
Manufacturer Part Number
LPC47M172
Description
ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
Manufacturer
SMSC Corporation
Datasheet
1.LPC47M172.pdf
(227 pages)
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.4.10 Digital Input Register (DIR)
PC-AT Mode
BIT 0 – 6 UNDEFINED
BIT 7 DSKCHG
PS/2 Mode
BIT 0 nHIGH DENS
BITS 1 – 2 DATA RATE SELECT
BITS 3 – 6 UNDEFINED
BIT 7 DSKCHG
Model 30 Mode
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Address 3F7 READ ONLY
This register is read-only in all modes.
The data bus outputs D0 – 6 are read as ‘0’.
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime
register at offset 0x18).
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and
300 Kbps are selected.
These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250
Kbps after a hardware reset.
Always read as a logic “1”
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime
register at offset 0x18).
RESET
RESET
RESET
COND.
COND.
COND.
DSK CHG
CHG
CHG
DSK
DSK
N/A
N/A
N/A
7
7
7
N/A
N/A
6
0
6
1
6
0
0
DATASHEET
N/A
N/A
5
0
5
1
5
0
0
Page 48
N/A
N/A
4
0
4
1
4
0
0
DMAEN NOPREC DRATE
N/A
N/A
3
0
3
1
3
0
DRATE
SEL1
N/A
N/A
2
0
2
2
0
DRATE
SEL0
SEL1
N/A
N/A
1
0
1
1
1
DRATE
nHIGH
DENS
SEL0
N/A
SMSC LPC47M172
0
0
0
1
0
0
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