LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 137

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

7.34
Note:
SMSC LPC47M172
See Table 13.2 for nPCI_RSTOUT and nPCI_RSTOUT2 timings.
Voltage Translation Circuit
The DDC_5V signals require external pull-up to VCC5V. The DDC_3V signals require external pull-up to
VCC. If DDC functions are selected on the pins, the pins will tri-state when VCC is removed.
The VGA DDC voltage translation circuitry is used in conjunction with integrated VGA chipsets. Since the
chipset operates at 3.3V signal levels and the VGA signals are specified at 5V signal levels, on-board
voltage translation is needed for the DDC signals. This is a non-inverting translation. See the Table 7.32
and Table 7.33 for further details on the logic.
The DDC data pins and the DDC clock pins function as inputs shorted together through the isolation
resistor. The DDC signals require external pull-up resistors on LPC47M172. See the “Pins That Require
External Resistors” section for resistor values. See Figure 7.10 for recommended schematic
implementation. Note the switch is always on after the DDC functions are selected on the GPIO pins. That
is, the switch is controlled by the GPIO alternate function select bits. Once the DDC functions are
selected, the switch is closed and remains closed when VCC is removed. The current flow is controlled by
the external signals on the DDC pins. See the tables below for the current flow across the switch based
on the voltage levels on the pins. The switch provides a 25ohm resistance to ground.
This circuit requires ESD protection external to the chip to protect the device from hot-plugging on the VGA
connector. See the “Electrical Characteristics” section for current and voltage requirements.
Due to the multiplexing with GPIO pins, these pins are powered by VTR. (Without the multiplexing
requirement, these pins could be powered by VCC).
DDCSDA_5V/ GP20
DDCSCL_5V/ GP21
DDCSDA_3V/ GP22
DDCSCL_3V/ GP23
nPCIRST_OUT
nPCIRST_OUT2
nPCI_RESET
NAME
Table 7.30 - nPCIRST_OUT and nPCIRST_OUT2 Truth Table
NAME
INPUT
0
1
Table 7.31 - Voltage Translation DDC Pins
Table 7.29 - nPCIRST_OUT Pins
IO_SW
IO_SW
IO_SW
IO_SW
OP14
OP14
BUFFER
BUFFER
DATASHEET
nPCIRST_OUT
Page 137
POWER
VTR
VTR
VTR
VTR
VTR
VTR
POWER
WELL
0
1
WELL
OUTPUTS
Buffered PCI Reset Output
Buffered PCI Reset Output
5V DDC Data IOD/ GPIO
(Note)
5V DDC Clock IOD/ GPIO
(Note )
3.3V DDC Data IOD/ GPIO
(Note)
3.3V DDC Clock IOD/ GPIO
(Note)
Advanced I/O Controller with Motherboard GLUE Logic
DESCRIPTION
DESCRIPTION
nPCIRST_OUT2
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
0
1
Datasheet