LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 8

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 13
Chapter 14
Chapter 15
Chapter 16
List Of Figures
Figure 2.1 - LPC47M172 Pin Layout ............................................................................................................................13
Figure 4.1 - LPC47M172 Block Diagram......................................................................................................................29
Figure 7.1 - NKBDRST Circuit....................................................................................................................................121
Figure 7.2 - Keyboard Latch.......................................................................................................................................122
Figure 7.3 - Mouse Latch ...........................................................................................................................................122
Figure 7.4 - GPIO Function Illustration.......................................................................................................................127
Figure 7.5 - Fan Tachometer Input and Clock Source ...............................................................................................131
Figure 7.6 - NHD_LED Circuit ....................................................................................................................................133
Figure 7.7 - YLW_LED/GRN_LED Circuit ..................................................................................................................134
Figure 7.8 - REF5V Circuit .........................................................................................................................................135
Figure 7.9 - REF5V_STBY.........................................................................................................................................136
Figure 7.10 - VGA DDC Voltage Translation Circuit...................................................................................................139
Figure 7.11 - SMBUS Isolation Circuit........................................................................................................................140
Figure 7.12 - PWRGD_3V Circuit, Discrete Implementation ......................................................................................142
Figure 7.13 - PWRGD_3V Circuit in LPC47M172 ......................................................................................................142
Figure 7.14 - NFPRST Timing....................................................................................................................................143
Figure 7.15 - SCK_BJT_Gate Circuit .........................................................................................................................144
Figure 7.16 - Backfeed Cut and Latched Backfeed Cut Circuit ..................................................................................145
Figure 7.17 - Latched Backfeed Cut Power Up Sequence.........................................................................................146
Figure 7.18 - Latched Backfeed Cut Sequence 1 ......................................................................................................146
Figure 7.19 - Latched Backfeed Cut Sequence 2 ......................................................................................................147
Figure 7.20 - Latched Backfeed Cut Flowchart ..........................................................................................................148
Figure 7.21 - CNR Circuit ...........................................................................................................................................150
Figure 13.1 - Power-Up Timing ..................................................................................................................................204
Figure 13.2 - Input Clock Timing ................................................................................................................................205
Figure 13.3 - PCI Clock Timing ..................................................................................................................................205
Figure 13.4 - Reset Timing.........................................................................................................................................205
Figure 13.5 - Output Timing Measurement Conditions, LPC Signals .........................................................................206
Figure 13.6 - Input Timing Measurement Conditions, LPC Signals............................................................................206
Figure 13.7 - I/O Write................................................................................................................................................206
Figure 13.8 - I/O Read ...............................................................................................................................................207
Figure 13.9 - DMA Request Assertion through NLDRQ .............................................................................................207
Figure 13.10 - DMA Write (First Byte) ........................................................................................................................207
Figure 13.11 - DMA Read (First Byte)........................................................................................................................207
Figure 13.12 - Floppy Disk Drive Timing (At Mode Only) ...........................................................................................208
Figure 13.13 - EPP 1.9 Data or Address Write Cycle.................................................................................................209
Figure 13.14 - EPP 1.9 Data or Address Read Cycle ................................................................................................210
Figure 13.15 - EPP 1.7 Data or Address Write Cycle.................................................................................................211
Figure 13.16 - EPP 1.7 Data or Address Read Cycle ................................................................................................211
Figure 13.17 - Parallel Port FIFO Timing ...................................................................................................................213
Figure 13.18 - ECP Parallel Port Forward Timing ......................................................................................................214
Figure 13.19 - ECP Parallel Port Reverse Timing ......................................................................................................215
Figure 13.20 - Setup and Hold Time ..........................................................................................................................216
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
12.4
13.1
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.6
13.1.7
Capacitance Values for Pins.................................................................................................................202
ECP Parallel Port Timing ......................................................................................................................212
Timing Diagrams ................................................................................................................203
Package Outline ................................................................................................................. 224
Board Test Mode................................................................................................................225
Reference Documents........................................................................................................ 227
Parallel Port FIFO (Mode 101).......................................................................................................212
ECP Parallel Port Timing ...............................................................................................................212
Forward-Idle ..................................................................................................................................212
Forward Data Transfer Phase .......................................................................................................212
Reverse-Idle Phase .......................................................................................................................212
Reverse Data Transfer Phase .......................................................................................................212
Output Drivers ...............................................................................................................................213
DATASHEET
Page 8
SMSC LPC47M172