LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 18

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
26
27
28
30
32
118
119
120
PIN#
nRTS1
TXD1
nCTS1
nDTR1
(XOR)
nRI1
nRI2
RXD2
TXD2
(NOTE 1)
NAME
Active low Request to Send output for the
Serial Port. Handshake output signal
notifies modem that the UART is ready to
transmit data. This signal can be
programmed by writing to bit 1 of the
Modem Control Register (MCR). The
hardware reset will reset the nRTS signal
to inactive mode (high). nRTS is forced
inactive during loop mode operation.
Transmit serial data output.
Active low Clear to Send input for the
serial port. Handshake signal that notifies
the UART that the modem is ready to
receive data. The CPU can monitor the
status of nCTS signal by reading bit 4 of
Modem Status Register (MSR). A nCTS
signal state change from low to high after
the last MSR read will set MSR bit 0 to a
1. If bit 3 of the Interrupt Enable Register
is set, the interrupt is generated when
nCTS changes state. The nCTS signal
has no effect on the transmitter.
Note: Bit 4 of MSR is the complement of
nCTS.
Active low Data Terminal Ready output
for the serial port. Handshake output
signal notifies modem that the UART is
ready to establish data communication
link. This signal can be programmed by
writing to bit 0 of Modem Control Register
(MCR). The hardware reset will reset the
nDTR signal to inactive mode (high).
nDTR is forced inactive during loop mode
operation.
XOR Chain Output.
Active low Ring Indicator input for the
serial port. Handshake signal that notifies
the UART that the telephone ring signal is
detected by the modem. The CPU can
monitor the status of nRI signal by
reading bit 6 of Modem Status Register
(MSR). A nRI signal state change from
low to high after the last MSR read will set
MSR bit 2 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nRI changes state.
Note: Bit 6 of MSR is the complement of
nRI.
Active low Ring Indicator input for serial
port 2. See description for nRI1.
Receiver serial data input.
Transmit serial data output.
SERIAL PORT 2 INTERFACE (8)
DESCRIPTION
DATASHEET
Page 18
O8
O12
I
O8
I
IPD
ISPD_400
O12
(NOTE 2)
BUFFER
NAME
VCC
VCC
VCC
VCC
VTR
VTR
VCC
VCC
(NOTE 3)
WELL
PWR
SMSC LPC47M172
6
6, 10
NOTES