LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 166

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
PME_EN2
Default = 0x00
PME_EN1
Default = 0x00
N/A
on VTR POR
on VTR POR
NAME
REG OFFSET
(Type)
(R/W)
(R/W)
0x0D
0x0E
0x0F
(R)
PME Wake Enable Register 2
This register is used to enable individual LPC47M172 PME wake sources
onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”),
if the source asserts a wake event so that the associated status bit is “1”
and the PME_En bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive
(“0”), the PME Wake Status register will indicate the state of the wake
source but will not assert the nIO_PME signal.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or HARD RESET.
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”),
if the source asserts a wake event so that the associated status bit is “1”
and the PME_En bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive
(“0”), the PME Wake Status register will indicate the state of the wake
source but will not assert the nIO_PME signal.
Bit[0] Reserved (Note 1)
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] SPEKEY (Wake on specific key)
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or HARD RESET.
Bits[7:0] Reserved – reads return 0
DATASHEET
Page 166
DESCRIPTION
SMSC LPC47M172