LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 111

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

7.21.5 Programmed I/O - Transfers from the Host to the FIFO
7.22
7.23
7.23.1 Timing Diagrams For SER_IRQ Cycle
Note:
SMSC LPC47M172
PCI_CLK
SER_IRQ
Drive Source
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or
equal to (16-<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in
the FIFO). The host must respond to the request by reading data from the FIFO. This process is repeated
until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be completely emptied
in a single burst, otherwise a minimum of (16-<threshold>) bytes may be read from the FIFO in a single
burst.
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more
bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty
bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes.
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to
<threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in
the FIFO.) The host must respond to the request by writing data to the FIFO. If at this time the FIFO is
empty, it can be completely filled in a single burst, otherwise a minimum of (16-<threshold>) bytes may be
written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the
FIFO.
Power Management
Direct power management capability is provided for the following logical devices: floppy disk, UART, and
the parallel port. Direct power management is controlled by CR22. Refer to CR22 in Table 11.3 for more
information.
Note on FDC Direct Powerdown: The Direct powerdown mode requires at least 8us delay at 250K
bits/sec configuration and 4us delay at 500K bits/sec. The delay should be added so that the
internal microcontroller can prepare itself to accept commands.
Serial IRQ
The LPC47M172 supports the serial interrupt to transmit interrupt information to the host system. The
serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
A) Start Frame timing with source sampled a low pulse on IRQ1
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
IRQ1
SL
or
H
writeIntrThreshold
START
Host Controller
START FRAME
H
1
DATASHEET
R
=
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T
(16-<threshold>) free bytes in FIFO
IRQ0 FRAME IRQ1 FRAME
S
None
R
T
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
S
IRQ1
R
T
IRQ2 FRAME
S
None
R
T
Datasheet