LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 76

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
*Note:
6.28.2 Receive Buffer Register (RB)
6.28.3 Transmit Buffer Register (TB)
6.28.4 Interrupt Enable Register (IER)
Bit 0
Bit 1
Bit 2
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
DLAB is Bit 7 of the Line Control Register
The following section describes the operation of the registers.
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted
and received first. Received data is double buffered; this uses an additional shift register to receive the
serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register.
The shift register is not accessible.
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an
additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register
is loaded from the Transmit Buffer when the transmission of the previous byte is complete.
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the enables of the five interrupt sources of the Serial Port
interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register.
Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled.
Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port
interrupt out of the LPC47M172. All other system functions operate in their normal manner, including the
Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described
below.
This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set
to logic “1”.
This bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”.
This bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the
interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the
source.
DLAB*
X
1
1
A2
1
0
0
A1
1
0
0
DATASHEET
A0
1
0
1
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Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
REGISTER NAME
SMSC LPC47M172