LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 187

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

11.4
SMSC LPC47M172
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
LOGICAL
NUMBER
DEVICE
Logical Device I/O Address
Table 11.7 and Table 11.8 summarize the logical device I/O addresses when LD_NUM bit is 0 and 1.
FDC
Parallel
Port
Serial Port 2
Serial Port
Power Control
Mouse
KYBD
GPIO
LOGICAL
DEVICE
Table 11.7 - Logical Device I/O Address, LD_NUM Bit = 0
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
n/a
n/a
0x60,0x61
REGISTER
INDEX
DATASHEET
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
[0x0100:0x0FFC]
ON 4 BYTE BOUNDARIES
(EPP Not supported)
or
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
(all modes supported,
EPP is only available when
the base address is on an 8-
byte boundary)
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
[0x0000:0x0FE0]
on 32-byte boundaries
Not Relocatable
Not Relocatable
Fixed Base Address: 60,64
[0x0000:0x0FE0]
on 32-byte boundaries
Page 187
BASE I/O
(NOTE 1)
RANGE
Advanced I/O Controller with Motherboard GLUE Logic
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TSR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h : cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+00 : PME Status
.
.
.
+1F : Reserved
(See Table 8.1 for Full List)
+0 : Data Register
+4 : Command/Status Reg.
+0 : Data Register
+4 : Command/Status Reg.
+00 : GP10
.
.
+1F : Reserved
(See Table 9.1 for Full List)
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
BASE OFFSETS
FIXED
Datasheet