LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 85

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

6.29.3 FIFO Polled Mode Operation
Note
Note
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
1
2
:
:
BAUD RATE
With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of
operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the
polled mode of operation. In this mode, the user’s program will check RCVR and XMITTER status via the
LSR. LSR definitions for the FIFO Polled Mode are as follows:
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the
RCVR and XMIT FIFOs are still fully capable of holding characters.
DESIRED
The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
The High Speed bit is located in the Device Configuration Space.
115200
230400
460800
19200
38400
57600
134.5
1200
1800
2000
2400
3600
4800
7200
9600
110
150
300
600
50
75
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way
as when in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
GENERATE 16X CLOCK
DIVISOR USED TO
32770
32769
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
DATASHEET
Table 6.30 - Baud Rates
Page 85
BETWEEN DESIRED AND ACTUAL
PERCENT ERROR DIFFERENCE
0.001
0.004
0.005
0.030
0.16
0.16
0.16
0.16
Advanced I/O Controller with Motherboard GLUE Logic
-
-
-
-
-
-
-
-
-
-
-
-
-
1
SPEED BIT
HIGH
SMSC LPC47M172
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
Datasheet
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