CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 86

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.6.4.1 Tx Path Details
1999 Consumer Microcircuits Limited
(R3/C3 for Tx, R2/C2 for Rx, as shown in Figures 2a and b) are also scaled with MCLK. For the case
of MCLK = 8.192MHz, this means increasing the RC products by approximately 10%.
There is a small attenuation caused by two pole on-chip continuous time filters in both the Tx and Rx,
which do not scale with MCLK. This will cause attenuation at 10kHz of between 0.05dB and 0.15dB in
the Rx (this can be bypassed), and between 0.03dB and 0.08dB in the Tx. This effect can be ignored
in many applications, but is described here for completeness.
Data can be input either via the DQPSK modulator or via the direct write port at a symbol rate of
MCLK/512. Due to the zero padding of the data from symbol rate to 8x sample rate, the ratio of
symbol rate to MCLK rate is fixed.
I and Q Data is passed through the following elements:
The reconstruction filter has significant attenuation in the passband, with the following characteristic
(including the external RC):
This attenuation is compensated in the default filter coefficients by convolving the required FIR
response with a 15-tap pre-emphasis FIR filter. The reconstruction filter and the FIR filters will track
with the MCLK frequency, provided that the external RC is scaled in proportion. The FIR filter
approximately cancels the reconstruction filter attenuation up to a frequency of MCLK/900.
Coefficients of the pre-emphasis FIR filter used in the default filter coefficients are shown below.
If there is no source of attenuation or phase distortion external to the IC for which the user wishes to
compensate, this filter can be combined with the main shaping filter as described in Section 1.6.4. If
a) a pair of programmable FIR filters (79-tap and 63-tap)
b) a gain/phase/offset adjustment block
c) a matched pair of sigma delta DACs and
d) a two pole continuous time active filter which suppresses clock noise. This has a fixed
MCLK/Freq
Attenuation (dB)
-0.00737876
-0.00987614
-0.0150585
-0.0206503
-0.0260154
-0.0304823
-0.0334478
1.22444
-0.0334478
-0.0304823
-0.0260154
-0.0206503
-0.0150585
-0.00987614
-0.00737876
a switched capacitor data reconstruction filter (which requires one external RC pole).
pole frequency of 140kHz (subject to
significant effect on the passband for all allowable MCLK frequencies, but the level of
clock noise suppression supplied by this filter (48dB for MCLK = 9.216MHz) is reduced
at lower MCLK frequencies.
0
0
4608
0.1
86
2304
0.4
40% tolerance for process variations). It has no
1536
0.9
1152
1.6
1024
2.1
922
2.6
CMX980A
D/980A/3