CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 41

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Title:
Address:
Function:
Description:
7:6
5:3
Bit
2
1
0
1999 Consumer Microcircuits Limited
RamDacRate
RamDacInc
AutoCycle
RamDacActive
RamDacCtrl
RamDac Control register
$0x0C
RW
This register controls the operation of DAC 1, together with the operation of the memory
(DacSram) which can be used to drive the digital input of DAC 1.
Name
High
High
High
High
Active State
RamDacCtrl[5:3]
RW
RW
RW
RW
RW
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Ram Dac Rate Select Table
Reserved. These bits should be set Low. Undefined on
read.
These three bits set the rate at which the RamDac
memory’s DAC access address pointer changes. The three
bit value (RamDacRate) causes a change rate of
2
This bit activates the RamDac memory scan operation.
Setting it active will cause the memory address to
increment up to the top (highest) location, conversely
setting the bit inactive will cause the memory address to
decrement down to the bottom location. If the bit is
changed while the memory is being scanned, the current
scan will complete before the new state of the RamDacInc
bit takes effect.
This bit is only valid if the RamDacActive bit is active.
When set active, the Auxiliary SRAM memory will be
continually scanned at the rate set by the RamDacRate
bits. This enables a symmetrical periodic waveform to be
driven out on the AUXDAC1 pin. The Auxiliary SRAM
address cycles from the bottom location up to the top
location, and back down to the bottom again.
DAC 1 input mode bit. When inactive, the AuxDacData
Registers (offsets 0 and 1) are used as the source for
conversion. If this bit is active, the DAC is driven from the
output of the RamDac memory.
RamDacRate
41
)
kHz. See table below.
Dac Update Frequency
(Relative to MCLK)
MCLK/512
MCLK/256
MCLK/128
MCLK/64
MCLK/32
MCLK/16
MCLK/8
MCLK/4
Function
(
36 x
CMX980A
D/980A/3