CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 59

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Title:
Address:
Function:
Description:
7:4
Bit
3
2
1
0
1999 Consumer Microcircuits Limited
0
1
RxIFClkStopMode
Aux_ClkStopMode
AutoClkStopMode
RxClkStop
ClkStopCtrl
Address field [6:0]
1
Clock-Stop Control register
$0x3C
RW
Control of power down and clock operation.
Name
1
1
0
Address and Data format for ClkStopCtrl access
High
High
High
High
0
Active State
RW
RW
RW
RW
RW
Reserved. These bits should be set Low. Undefined on
read.
When set active, this bit puts the Rx data serial-interface
logic into clock-stop mode. The interface will cease activity
and enter a power down state. It will remain in this state
until the user disables this bit.
When set active, this bit puts the auxiliary ADC and
RamDac logic into clock-stop mode. This reduces power
within this section when auxiliary functions are not in use.
When set active with the serial port configured at low data
rate (DataRateHi bit of ConfigCtrl1 Register set inactive
(Low)), this bit puts the serial interface logic into auto stop
mode. The interface will cease activity and enter a power
down state if no CmdFS activity is detected for 4096
master clock cycles (444µs with a 9.216MHz MCLK). To
re-start serial interface operations, the user asserts the
CmdFS strobe for at least one MCLK cycle.
When set active causes the RxEn bit of RxSetup1 Register
to gate the Rx Data path master clock. When inactive
(default state) the Rx Data path master clock is always
supplied.
R
59
R
R
R
D3 D2 D1 D0
Coefficient Data
Function
field [3:0]
CMX980A
D/980A/3