CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 85

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1999 Consumer Microcircuits Limited
Application Notes
Interrupt Handling
Interrupt handling requires an extra read to clear the source of the interrupt. Handling interrupts is
sometimes a source of confusion. The notes below are intended to clarify the operation of interrupts:
Tx FIFO status interrupts
These interrupts can only be cleared by first carrying out the appropriate action to stop the source of
the Tx FIFO interrupt (this would usually require writing some data to the Tx FIFO) and then carrying
out a further read on the TxFIFOStatus Register ($0x22) to reset the N_IRQ pin.
Tx/Rx FIR filter tap overflow and Gain, Phase and Offset overflow interrupts
A typical interrupt handling procedure for Tx (the same can be applied to Rx) would be:
Rx ADC I and Q channel overflow - due to excessive input amplitude interrupts
These interrupts will remain set until the source of the excessive amplitude has been reduced to below
the acceptable level. Once this has been achieved, the RxErrorStatus Register can be read in order
to reset the N_IRQ pin.
Note: Never enable these interrupts with the Rx path disabled, as this will continuously generate an
interrupt.
Configuration
Configuration registers ConfigCtrl1 and ConfigCtrl2 are not double buffered and so should not be
altered during Tx.
Reset
The N_RESET pin should be held active (Low) during power-up. The N_RESET pin requires two
complete MCLK clock cycles whilst active in order to take effect.
If it is required to re-optimise FIR filter coefficients for a different application, or to compensate for the
behaviour of components external to the CMX980A, the default coefficients can be overwritten. There
are many ways to develop FIR filter coefficients for a non-TETRA application.
The basic algorithm is to take the required frequency domain response, apply an inverse Fourier
transform and use a windowing function to reduce the impulse response to the desired length. The
impulse response is then identical to the required FIR coefficients. In the case of the CMX980A, both
transmit and receive filters are configured as two cascaded filters. When developing customised
coefficients, the user has a choice of whether to design the two filters separately or to develop a single
filter and then factorise the resultant polynomial in Z (representing the impulse response of the overall
FIR filter) into two shorter polynomials of appropriate length. Various commercial and public domain
software is available which may help with this process.
In order to develop optimal FIR filter coefficients for the CMX980A, knowledge of the non-
programmable filters in the design is required, together with a more detailed understanding of the
function of certain external components. Please refer to the block diagram in Figure 1 and the
external component diagrams in Figures 2a and 2b.
The combined effect of all of the filters in the Tx or Rx, when using default FIR coefficients, is to give a
linear phase root raised cosine filter shape, with a symbol rate of MCLK/512 and
Developing and Optimising FIR Filter Coefficients
= 0.35. This tracks fairly well with MCLK frequency, provided that the dominant external RC poles
Read TxErrorStatus Register ($0x0E) and confirm that a Tx FIR filter error has occurred.
This will reset the N_IRQ pin.
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CMX980A
D/980A/3