CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 51

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Title:
Address:
Function:
Description:
Bit
7
6
5
4
3
2
1
0
1999 Consumer Microcircuits Limited
TxPathEn
FIFOUnderRead
FIFOOverWrite
FIFONotFull
FIFONearlyFull
FIFONearlyEmpty
FIFOEmpty
FifoIrqActive
TxFIFOStatus
Transmit data FIFO Status register
$0x22
R
This register is the Tx Data FIFO status register. The TxIrqActive bit is set active when one of
the other bits in this register is the source of an interrupt event. Some of these status conditions
are caused by transitory events, therefore their state is latched (marked with an ‘L’). The bits
marked with a parenthesised ‘L’ are only latched in their interrupt generation state if their
associated mask bit is inactive. Reading this status register causes all latched bits to be set
inactive, unless an error event is currently pending.
Setting any bit of this register High will cause an interrupt to be generated (N_IRQ will be set
Low) if the source of the interrupt has not been masked in the corresponding Mask register.
Name
Low
High
High
High
High
High
High
Active State
High
R(L)
RL
RL
R(L)
R(L)
R(L)
R(L)
RL
51
This interrupt is generated when the FIFO
contains one remaining data entry and 3 locations
are free.
When High this bit shows that the Tx Data path is
currently active, enabling the user to confirm
whether ramp down has completed. For interrupt
generation purposes, a logic Low on this bit will
be considered as active. However, un-masking
the interrupt on this bit will generally appear to
invert the read status. This is because the read
operation is switched from the active low source
signal to an active high output latch which stores
the last (uncleared) interrupt state.
Error status bit. When active indicates a read
from the FIFO occurred while the FIFO was
empty.
Error status bit. When active indicates a write to
the FIFO occurred while the FIFO was full.
Most significant FIFO length status bit.
High, this bit indicates the FIFO is not full. For
interrupt generation purposes, a logic High on this
bit will be considered as active.
This interrupt is generated when the FIFO
contains 3 used locations and one remains
available
When active indicates the FIFO is empty.
This bit is set High if there is an active interrupt
caused by one of the status bits in this register.
Function
CMX980A
D/980A/3
When