CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 49

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Title:
Address:
Function:
Description:
Bit
7
6
5
4
3
2
1
0
1999 Consumer Microcircuits Limited
RxDataPathQOF
RxDataPathIOF
AdcQOF
AdcIOF
RxLowPassOF
RxRRCOF
EvenSamplePhase
RxIrqActive
RxErrorStatus
Receive Error Status register.
$0x20
R
This register is the Rx Data path error status register. The RxIrqActive bit is set active when one
of the other bits in this register is the source of an interrupt event. All these error conditions are
caused by transitory events, therefore the error condition is latched (marked with an ‘L’).
Reading this status register causes all latched bits to be set inactive unless an error event is
currently pending.
Setting any bit of this register High will cause an interrupt to be generated (N_IRQ will be set
Low) if the source of the interrupt has not been masked in the corresponding Mask register.
Name
0
1
Address field [6:0]
High
High
High
High
High
High
High
High
Active State
0
Address and Data format for RxErrorStatus access
0
RL
RL
RL
RL
RL
RL
RL
RL
0
0
Data path gain, phase and offset (GPO) adjustment unit:
Q channel overflow error status bit.
Data path gain, phase and offset (GPO) adjustment unit:
I channel overflow error status bit.
ADC Q channel overflow error due to excessive input
amplitude.
ADC I channel overflow error due to excessive input
amplitude.
63-tap Low-pass I and Q filter data accumulator overflow
error status bit.
63-tap RRC I and Q filter data accumulator overflow error
status bit.
When this status bit is active, the associated interrupt may
be used to re-synchronise the Rx data if for any reason
data synchronisation is lost. If the corresponding mask bit
is set inactive, an interrupt will be generated on the next
Q-phase data in the Rx output register. The next falling
edge of SClk with RxFS High indicates the LSB of the Q
channel data. The mask bit should be disabled after this to
prevent continuous Q-phase interrupts.
This bit is set High if there is an active interrupt caused by
one of the status bits in this register.
0
49
D7 D6 D5 D4 D3 D2
Data field [7:0]
Function
D1 D0
CMX980A
D/980A/3