CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 13

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.5.4
1.5.4.1 Anti-Alias Filtering and Sigma-Delta A-D Converters
1.5.4.2 Rx FIR Filters
1.5.4.3 Offset Registers
1.5.4.4 I and Q Channel Gain
1999 Consumer Microcircuits Limited
output, but any adverse change in the in-band gain and group delay performance will have to be
compensated prior to loading the data into the IC.
Rx Data Path
The sampling frequency of the Sigma-Delta A-D is 128x symbol rate. The high oversampling rate
relaxes the design requirements on the anti-alias filter. However, to achieve optimum performance the
anti-alias filter must reject the sampling frequency to about -110dB, of which at least 30dB must be
provided externally. Additionally, in order to ease the complexity of the subsequent digital filters, there
is a further requirement that the anti-alias filter suppress 8x symbol rate to about
-15dB. The on-chip anti-alias filter is designed to achieve this when used in conjunction with some
external filtering. If required, the on-chip anti-alias filter can be by-passed and powered down, although
external anti-aliasing must then be provided. The fourth-order Sigma-Delta A-D converters are
designed to have low distortion and >96dB dynamic range. The baseband I and Q channels must be
provided as differential signals; this minimises in-band pick up both on and off the chip.
Both I and Q Sigma-Delta converters produce a single bit output sampled at MCLK/4. This data is
passed to a non-programmable decimation FIR filter, which is sampled at MCLK/4 and gives sufficient
rejection at 8x symbol rate (MCLK/64) to permit decimation to that frequency (note that around -30dB
is provided by the primary anti-alias filters).
Digital filtering is applied to the data from the Sigma-Delta A-D converter decimation filters by two 63-
tap FIR filters in cascade. The default coefficients are set to give a Root Raised Cosine response with
roll-off factor ( ) of 0.35. The first filter is used to enhance stop-band rejection, while the second filter
provides the primary shaping requirements for root raised cosine response.
System generated offsets may be removed by control of the offset register via the serial interface.
Programmable gain modules are provided in both I and Q channels. These blocks allow the user to
adjust the dynamic range of the received data within the digital filters, thus optimising the filter signal
to noise performance for a range of levels at the Rx input pins. In the receive section the gain-
multiplier sign bit is user accessible, therefore phase inversion in each channel is possible by
programming negative numbers into the gain registers.
The two channels are independently programmable. This enables differential gain corrections to be
made within the digital domain.
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CMX980A
D/980A/3