CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 20

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.5.7.6 Coefficient Memory
1.5.7.7 Auto Power Save Mode
1999 Consumer Microcircuits Limited
The convention for naming filter coefficients is A1 to An, where n is given by the filter tap length, i.e.
for a 63-tap filter, n = 63. Within the filter architecture, location A0 has a special purpose and must
contain zero for correct operation of the computational algorithm. The internal architecture of the 63-
tap filters allows access to all coefficients, but the default values are symmetrical about the central
coefficient to provide linear phase response. The user is free to write non-symmetrical values, giving
the possibility of non-linear phase correction for off-chip components in these filters. The Tx 79-tap
filter differs by having coefficients A1 to A40 only, taking advantage of the filter symmetry to reduce
its RAM size. Thus write or read operations beyond the A40 coefficient number will be reflected about
the central coefficient e.g. the 47th read operation from the 79-tap filter would access coefficient
location A33 (80-47).
To access the coefficient RAMs, the user asserts the CoeffRamIoEn bit in the ConfigCtrl2 Register,
then performs the operation (read or write) to the MSB of the required FIR filter. The first access after
the CoeffRamIoEn bit goes high is directed to location A1. Completing the coefficient access, by
addressing the LSB,
repeated until the required number of locations has been accessed.
There is no practical reason to write or read beyond location A40 in the 79-tap filter, but in any case
the user must avoid write operations at the (Filter Length + 1) location in any filter. As previously
stated this location must be zero for the filters to operate correctly.
Note that filter coefficient read/write operations should be performed with the appropriate path (Tx or
Rx) disabled, but the clock stop bits must NOT be set.
The global reset (N_RESET pin) forces the default coefficients in all filters when asserted (Low).
By setting the AutoClkStopMode bit in the ClkStopCtrl Register, the serial interface will enter an
automatic power down mode. In this mode, if no serial port activity on the CmdFS is detected after a
time out (TMO) period the serial interface will enter a standby state. In this state all master clock
activity within the interface is stopped (to reduce power to a minimum) and the SClk pin stops in the
high state. It will remain in this state until the user asserts the CmdFS pin for at least one MCLK cycle
time, when normal serial port activity will recommence and serial port operation can continue as
normal. Subsequent periods of TMO without CmdFS activity will cause the serial interface to enter
power down mode again.
The time out period TMO is fixed internally to 4096 master clock periods (444µs when using a
9.216MHz master clock).
When in the power down state and the SClk pin is high, the CmdFS pin may be asserted
asynchronously but, when the SClk re-starts, subsequent CmdFS strobes must respect the timing
constraints given in the timing section of this document. The serial interface is stopped in the state
where it tests the CmdFS pin for a high state, so re-starting from this point by asserting CmdFS will
begin a serial operation cycle in the interface logic.
Applying global reset whilst in the power down state will return the device to normal serial mode.
The use of Auto Power Save mode, by setting the AutoClkStopMode bit, is available only in low data
rate mode (set DataRateHi bit of ConfigCtrl1 Register inactive), as this mode is envisaged for use in
low speed/low power applications. However, systems that use high data rate mode can make use of
this facility by setting a low data rate (set DataRateHi bit of ConfigCtrl1 Register inactive) before
asserting the AutoClkStopMode bit, then returning to the high data rate mode by setting the
DataRateHi bit active.
automatically moves the Coefficient Ram Pointer to A2.
20
The process is
CMX980A
D/980A/3