CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 70

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Title:
Address:
Function:
Description:
7:0
7:6
5:0
7:0
7:6
5:0
Bit
1999 Consumer Microcircuits Limited
TxDPIDataLSB
TxDPIDataMSB
TxDPQDataLSB
TxDPQDataMSB
TxDataAccess
Tx Data path Access point.
$0x50 to $0x53 (mapped over 4 locations)
RW
This register block allows direct access to the Tx Data path values just after the gain, phase and
offset adjustment block. Both read and write operations are permitted. A read operation reads
the signal values on the I and Q channels. A write operation will write data directly to the Sigma-
Delta DAC input. To prevent normal Tx data overwriting this value the TxDPAccessSel bit in the
LoopBackCtrl Register should be set active. The MSB read data register is buffered to enable
access to a discrete sample value (if this register was not buffered, data from different sample
periods could be in the MSB and LSB registers). Therefore the LSB register must be read first
for correct operation.
Name
Address $0x50
Address $0x51
Address $0x52
Address $0x53
Data
Data
Data
Data
Active State
RW
RW
RW
RW
RW
RW
Least significant 8 bits of the TxDPIData register. This
register must be read before its associated MSB register.
Reserved. Set these bits Low. Undefined on read.
Most significant 6 bits of the TxDPIData register.
Least significant 8 bits of the TxDPQData register. This
register must be read before its associated MSB register.
Reserved. Set these bits Low. Undefined on read.
Most significant 6 bits of the TxDPQData register.
70
Function
CMX980A
D/980A/3