CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 33

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Title:
Address:
Function:
Description:
Bit
7
6
5
4
3
2
1
1999 Consumer Microcircuits Limited
Rx32BitMode
RxSampleSel
RxIdentMode
RxEn
RxBistActive
AnaAdcReset
AnaEnAutoReset
RxSetup1
First Receive Setup control register
$0x08
RW
Receive path setup and initialisation control bits.
Name
High
Data
High
High
High
Pulse
Low
Active State
RW
RW
RW
RW
RW
W
R
RW
When set active, the Rx port operates on 32-bit frames -
I data in the MSB word, Q data in the LSB word.
This bit is used to select which pair of I,Q samples is
supplied from the possible two pairs when the DataRateHi
bit in ConfigCtrl1 Register is in the low mode (inactive). It
has no effect when DataRateHi is active. When set High,
this bit selects odd-numbered samples (I
and when set Low this bit selects the even-numbered
samples, where the sampling starts with (I
is set active.
When asserted this bit causes the received data to carry an
identification bit in the lsb of the data word. Q channel data
is identified by a logic ‘1’ and I channel data by the internal
symbol clock phase, which is logic ‘0’ for seven out of eight
samples and logic ‘1’ for the other sample. In low data rate
mode, the symbol clock may coincide with the discarded
symbol; this can be rectified by toggling the RxSampleSel
bit. The received data dynamic range is therefore reduced
from 16 to 15 bits in this mode. The user can swap modes
during a receive data burst without affecting Rx operations.
When set active, enables the Rx Data path, which then
processes the signals on the IRXP,IRXN and QRXP,QRXN
pins, outputting results via the RxData serial port. This bit
also acts as a receive section power enable bit.
When set active, enables Rx Built-In Self Test operation.
When this bit is set High, a 4-clock-cycle ADC auto reset
event is generated. It is not necessary to clear this bit
before another ADC auto reset event is initiated.
The read state of this bit indicates the logic level last written
to this bit. It does not have a functional significance and is
only available for test purposes.
When active this bit enables the ADC auto reset function.
On taking N_RESET Low, this bit is set active, which is the
default operating condition.
33
Function
1
, Q
0
, Q
1
), (I
0
) after RxEn
3
, Q
CMX980A
3
) etc.
D/980A/3