CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 18

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.5.7.5 Command Control Serial Word
1999 Consumer Microcircuits Limited
( 1 word remaining ) or when the FIFO is “nearly” full (1 location available). In each case, the user is
responsible for managing the response latency in detecting and servicing the interrupt and for writing
new data into the FIFO so that symbol ‘run-out’ does not occur.
Direct write to 79-tap filter mode
The FIFO and DQPSK modulator may be bypassed thus allowing the user direct access to the Tx
filter chain input. The 12-bit data words must be supplied to input holding registers at MCLK/512
samples/sec for both I and Q channels.
TxDirectWrite79tapI and TxDirectWrite79tapQ Registers are in the page 1 address map. By utilising
the four least significant address bits to map to the most significant bits of the data, a 12-bit data word
can be transferred in a single serial-write frame.
Power Ramping and Frame Interlock
The RampUp bit in the TxData word is used to control both the power ramping function and the frame
activation. To start a transmission frame, a transmission word is written with the RampUp bit active. All
subsequent TxData words prior to frame termination must also have this bit active. The frame is
terminated by writing transmit data words with the RampUp bit inactive. Subsequent TxData words
must also have this bit inactive, until initiation of a new frame is required. While the power ramping is
active (up or down) the user must supply transmission symbols or valid constellation points. Once the
ramp down operation has completed, all subsequent TxData writes with the RampUp bit inactive will
be ignored.
A command word either directly accesses an internal register for a read or write operation, or
addresses a memory access point to indirectly access a block of internal memory. For test purposes
all registers that can be written may also be read. Not all registers may be written, as some are just
status registers. Each register or memory access point is assigned a unique address: the whole (8-
bit) address range is reserved for the CMX980A.
A page address technique is used to extend the available address space beyond the 128 locations
allowed by 7-bit address fields.
(page 0 and page 1) are used. The device configuration and control registers ConfigCtrl1 and
ConfigCtrl2 are accessible across all pages, ConfigCtrl2 bits 6 and 7 forming the 2-bit page address.
Indirect Memory Addressing
All internal memory access is via an access point. First, a command word access is used to reset the
internal address pointer, then data port access operations post-increment this address pointer.
This gives four pages of 128 locations, of which the first two
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To allow a single serial-operation write, the
CMX980A
D/980A/3