CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 17

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1999 Consumer Microcircuits Limited
The eight points in the DQPSK constellation each have a magnitude of 1 and are spaced at 45
intervals around the unit circle. The default operating mode modulates two bit symbols into the TETRA
constellation by representing each symbol as a phase change, according to the following mapping,
where the left hand bit is considered as the first bit of the symbol and corresponds to bit 0, 2, 4 or 6 of
the TxData word (see the description in PAGE 0 ADDRESSED REGISTERS).
The user initiates a transmit frame by asserting the TxEn bit in the TxSetup Register. However,
internal transmission of the data will wait until specific conditions have been met. Firstly, a valid data
word must be written into the FIFO with the TxRampEn bit of the TxSetup Register asserted.
Secondly, the internal symbol clock must be active. Therefore there is a variable delay between
asserting the TxEn bit and transmission starting.
TxFIFOStatus Register to establish when transmission has started, and in this case the active state
of TxPathEn is High. In general, the user will wish to know when the transmit frame has completed.
This is indicated by TxPathEn returning Low.
To relieve the user of polling overheads when waiting for Tx frame completion, an interrupt can be set
up to occur on the transition of the TxPathEn bit from High to Low. In such circumstances, the
interrupt activation state of the TxPathEn can be considered Low.
Two control bits are associated with each data transmission word. One controls the format of the word
and the other initiates and terminates a transmission cycle. This close association enables precise
control of the transmission frame. To relieve the user of the need to synchronise each TxData write
with the internal transmit cycle, transmit data words are written into an internal 4-word-deep FIFO.
Symbols or constellation points are then read as needed from this FIFO. It is necessary to make sure
that there is always a word to be read, three data interlock mechanisms.
Data Interlock Mechanisms
There are three possible transmission data interlock mechanisms. It is recommended that the user
should always use one of these methods.
Software polling requires the user to first check that the FIFO is not full before writing each TxData
word. This may be accomplished by inspecting the relevant FIFO status bits before writing one or
more TxData words.
The Serial Clock when ready method is a hardware interlock mechanism (enabled by setting the
TxHandshakeEn bit of ConfigCtrl1 Register active). The mechanism allows the user to write TxData
words without doing any FIFO checks: the hardware handshake is implemented by stopping the serial
port clock when the FIFO is full. To prevent a serial port lockout-condition, the handshake is only
enabled once the transmission frame has been initiated and is automatically disabled at the end of a
frame. This mechanism should be used with care, because stopping the clock will freeze all other
serial port transfers (the serial port clock SClk is common to all three serial ports), including access to
auxiliary data converters and receive data.
Interrupt data demand is used to request data when the FIFO has reached a defined level. An
interrupt is generated when the data in the FIFO reaches the pre-defined level of “nearly” empty
Software polling
Serial Clock when ready
Interrupt data demand
1
0
0
1
Symbol
1
1
0
0
17
Phase Change
-135
+135
+45
-45
The user may poll the TxPathEn bit of the
CMX980A
D/980A/3