CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 23

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Page
78
78
70
66
68
70
66
68
64
65
72
72
80
79
81
62
83
85
1999 Consumer Microcircuits Limited
Note: Addresses $0x80 to $0xFF cannot be used as the MSB controls the direction of data flow:
$0x38-$0x39
$0x3A-$0x3B
$0x3D-$0x3F
$0x40-$0x41
$0x42-$0x43
$0x44-$0x45
$0x46-$0x47
$0x48-$0x49
$0x4A-$0x4B
$0x4C-$0x4D
$0x4E-$0x4F
$0x50-$0x51
$0x52-$0x53
$0x54-$0x5F
$0x60-$0x61
$0x62
$0x63
$0x64-$0x6D
$0x6E-$0x6F
$0x70-$0x73
$0x74-$0x7F
$0x10-$0x1F
$0x20-$0x2F
RxDataAccess
RxDataAccess
TxPhase
TxIQGainMult
TxIQOffset
TxPhase
TxIQGainMult
TxIQOffset
TxRampUpInc
TxRampDnDec
TxDataAccess
TxDataAccess
BISTPRSG
BISTControl
BISTCRCRegisters
SramData
DirectWrite79tapI
DirectWrite79tapQ
“1” = High = Read and “0” = Low = Write.
Direct Write Registers (Page 1)
SRAM Memory Access Points
Rx Data Path Access Points
Tx Data Path Access Points
Tx Data Path Registers
Self Test Registers
23
Receive path data access point (I)
Receive path data access point (Q)
Not Used
Transmit I channel phase correction registers
Transmit I channel gain attenuation registers
Transmit I channel offset correction registers
Transmit Q channel phase correction registers
Transmit Q channel gain attenuation registers
Transmit Q channel offset correction registers
Transmit ramp-up increment registers
Transmit ramp-down decrement registers
Transmit path data access point (I)
Transmit path data access point (Q)
Not Used
Built-in self test pseudo-random sequence generator
Built-in self test control register
Not Used
Built-in self test cyclic redundancy code checkers
Not Used
Auxiliary DAC1 memory I/O access addresses
Not Used
Direct write access to 79-tap I channel filter
Direct write access to 79-tap Q channel filter
CMX980A
D/980A/3