CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet
CMX980AL7
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CMX980AL7 Summary of contents
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D/980A/3 October 1999 1.0 Features RRC Filters for both Tx and Rx /4 DQPSK Modulation 2 x 14-Bit Resolution Sigma Delta D 16-Bit Resolution Sigma Delta A-D 1.1 Brief Description This device is intended to act as an ...
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TETRA Baseband Processor Section 1.0 FEATURES ....................................................................................................................................... 1 1.1 BRIEF DESCRIPTION....................................................................................................................... 1 1.2 BLOCK DIAGRAM ............................................................................................................................ 5 1.3 SIGNAL LIST .................................................................................................................................... 6 1.4 EXTERNAL COMPONENTS ............................................................................................................. 8 1.5 GENERAL DESCRIPTION ................................................................................................................ 9 1.5.1 Connection and Decoupling of Power Supplies................................................................... 9 ...
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TETRA Baseband Processor 1.6.4.1 Tx Path Details..................................................................................................................... 86 1.6.4.2 Rx Path Details .................................................................................................................... 87 1.6.4.3 General Procedure for Reconfiguring the CMX980A Filters .................................................. 88 1.6.5 Generating a Transmit Frame Sequence with optimal use of ramping features............... 88 1.6.6 Internal Symbol-Clock ...
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TETRA Baseband Processor 1999 Consumer Microcircuits Limited THIS PAGE DELIBERATELY LEFT BLANK 4 CMX980A D/980A/3 ...
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TETRA Baseband Processor 1.2 Block Diagram 1999 Consumer Microcircuits Limited Figure 1 Block Diagram 5 CMX980A D/980A/3 ...
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TETRA Baseband Processor 1.3 Signal List L6 Package L7 44 PLCC Package 44 QFP Pin No. Pin No ...
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TETRA Baseband Processor 1.3 Signal List (continued) L6 Package L7 44 PLCC Package 44 QFP Pin No. Pin No ...
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TETRA Baseband Processor 1.4 External Components Rx Inputs When using the internal anti-alias filter, the following is recommended: Example values (MCLK=9.216MHz 220 C1 = 1.5nF (R1, C1 precise values are not critical; -3dB at 240kHz 1.2k ...
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TETRA Baseband Processor 1.5 General Description The device is designed to operate at a master clock frequency of 9.216MHz, but may be used over the full specified frequency range provided that guidelines in this document are followed. Many internal functions ...
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TETRA Baseband Processor 1.5.2 Programmable FIR Filter Architecture Within both the transmit and receive data path a common FIR filter architecture for the implementation of the filtering requirements is employed. The filters use a small local static RAM for efficient ...
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TETRA Baseband Processor addition, to bypass this filter, the central coefficient (A40) should be chosen as “unity”, since this is the only unique coefficient. 1.5.3 Tx Data Path The features described below give a high degree of flexibility for the ...
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TETRA Baseband Processor incremented by the value TxRampUpInc until the count of 2047 (1.0) is reached, or decremented by the value in TxRampDnDec until zero is reached. In linear mode, this value (RCR) is used directly to provide the envelope ...
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TETRA Baseband Processor output, but any adverse change in the in-band gain and group delay performance will have to be compensated prior to loading the data into the IC. 1.5.4 Rx Data Path 1.5.4.1 Anti-Alias Filtering and Sigma-Delta A-D Converters ...
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TETRA Baseband Processor 1.5.5 Auxiliary Circuits 1.5.5.1 10-Bit DACs Four 10-bit DACs are provided to assist in a variety of control functions. The DACs are designed to provide an output as a proportion of the supply voltage, depending on the ...
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TETRA Baseband Processor 1.5.7 Serial Interface All digital data I/O and control functions for the CMX980A are via the serial interface expected that the CMX980A will be used in conjunction with a DSP and/or other processor. The device ...
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TETRA Baseband Processor 1.5.7.1 Command Interface A serial command word consists of a 16-bit frame. Each frame is marked by an active Frame Sync event which precedes the MSB bit. A command word can be either a control word or ...
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TETRA Baseband Processor The eight points in the DQPSK constellation each have a magnitude of 1 and are spaced at 45 intervals around the unit circle. The default operating mode modulates two bit symbols into the TETRA constellation by representing ...
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TETRA Baseband Processor ( 1 word remaining ) or when the FIFO is “nearly” full (1 location available). In each case, the user is responsible for managing the response latency in detecting and servicing the interrupt and for writing new ...
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TETRA Baseband Processor Example: To program the fifth and sixth locations of the Auxiliary SRAM with $0x01AA the commands would be: ; set ConfigCtrl1 all bits Low $0x8000 Cmd $0x8118 Cmd ; set ConfigCtrl2 bits 7 and 6 Low ; ...
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TETRA Baseband Processor 1.5.7.6 Coefficient Memory The convention for naming filter coefficients An, where n is given by the filter tap length, i.e. for a 63-tap filter 63. Within the filter architecture, location A0 has ...
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TETRA Baseband Processor 1.5.8 Register Description This section describes in detail each of the registers and access points addressed by the Command Control Serial Word. Key to Register Map Each section that follows describes in detail the operation and use ...
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TETRA Baseband Processor 1.5.8.1 Register and Access Point Summary Page 24 $0x00 ConfigCtrl1 ConfigCtrl2 26 $0x01 PowerDownCtrl 28 $0x02 TxSetup 29 $0x03 31 $0x04-$0x07 TxData RxSetup1 34 $0x08 36 $0x09 RxSetup2 37 $0x0A AnaCtrl AuxAdcCtrl 38 $0x0B 42 $0x0C RamDacCtrl ...
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TETRA Baseband Processor Page 78 $0x38-$0x39 RxDataAccess 78 $0x3A-$0x3B RxDataAccess $0x3D-$0x3F TxPhase 70 $0x40-$0x41 66 $0x42-$0x43 TxIQGainMult TxIQOffset 68 $0x44-$0x45 TxPhase 70 $0x46-$0x47 66 $0x48-$0x49 TxIQGainMult TxIQOffset 68 $0x4A-$0x4B 64 $0x4C-$0x4D TxRampUpInc 65 $0x4E-$0x4F TxRampDnDec TxDataAccess 72 $0x50-$0x51 TxDataAccess 72 ...
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TETRA Baseband Processor UNIVERSAL REGISTERS ACCESSIBLE IN ALL PAGES ConfigCtrl1 Title: Configuration Control register Address: $0x00 Function: RW Description: General configuration bits, together with operational control signal bits. Bit Name 7 DataRateHi 6 TxHandshakeEn 5 BiDirCmdPortEn 4 RxDataForCmdRdEn (5,4) CommandReadDataMode ...
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TETRA Baseband Processor Address and Data format for ConfigCtrl1 access Address field [6: 1999 Consumer Microcircuits Limited Data field [7:0] CMX980A D/980A/3 ...
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TETRA Baseband Processor ConfigCtrl2 Title: Configuration Control register Address: $0x01 Function: RW Description: General configuration bits, together with operational control signal bits. Bit Name Active State 7:6 PageAddress Data 5 n_SlowDown Low 4 SRamIoRdInc High 3 SRamloEn High 2 CoeffRamIoRdInc ...
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TETRA Baseband Processor Bit Name Active State 0 n_BigEndData Low Address and Data format for ConfigCtrl2 access Address field [6: 1999 Consumer Microcircuits Limited RW When set active causes serial port read data, from the Rx ...
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TETRA Baseband Processor PAGE 0 ADDRESSED REGISTERS PowerDownCtrl Title: Power Control register Address: $0x02 Function: RW Description: This register, together with the following bits, controls the power saving features: TxCtrlEn TxClkStop TxEn RxIFClkStopMode Aux_ClkStopMode AutoClkStopMode RxClkStop DataRateHi TxHandshakeEn RxEn Bit ...
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TETRA Baseband Processor TxSetup Title: Transmit Setup register Address: $0x03 Function: RW Description: Sets up the transmit functions. Bit Name Active State 7 6 TxCtrlEn Low 5 TxDirectWriteEn High 4 LinearRamp High 3 TxClkStop High 2 TxEn High 1 TxRampEn ...
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TETRA Baseband Processor TxData Title: Transmit Data register Address: $0x04 - $0x07 (Mapped over four locations, two address bits being used as data bits) Function: W FIFO input R FIFO output Description: This transmit data register is 10 bits wide. ...
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TETRA Baseband Processor Read operation Bit Name Active State Address $0x04 7:2 1:0 UpperFIFORdData Data Address $0x05 7:0 LowerFIFORdData Data Address $0x06 and $0x07 7:0 For these read operations to be valid, the Tx Data path must be active (TxEn ...
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TETRA Baseband Processor Address and Data format for TxData Write access Address field [6: Address and Data format for TxData (Modulator Bypass Mode) Write access Address field [6: Address field [6: ...
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TETRA Baseband Processor RxSetup1 Title: First Receive Setup control register Address: $0x08 Function: RW Description: Receive path setup and initialisation control bits. Bit Name Active State 7 Rx32BitMode High 6 RxSampleSel Data 5 RxIdentMode High 4 RxEn High 3 RxBistActive ...
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TETRA Baseband Processor Bit Name Active State 0 RxFirCoeffReset Low Address field [6: 1999 Consumer Microcircuits Limited RW When set active forces all the Rx Data path filters to load their default coefficient values. This bit ...
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TETRA Baseband Processor RxSetup2 Title: Second Receive Setup control register Address: $0x09 Function: RW Description: Receive I and Q vernier control bits. Bit Name Active State 7:4 QvernierDelay High 3:0 IvernierDelay High Note: The values are in the format of ...
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TETRA Baseband Processor AnaCtrl Title: Analogue configuration Control register Address: $0x0A Function: RW Description: Reserved. All bits should be set Low. 1999 Consumer Microcircuits Limited 36 CMX980A D/980A/3 ...
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TETRA Baseband Processor AuxAdcCtrl Title: Auxiliary ADC data converter Control register Address: $0x0B Function: RW Description: This register controls the operation of the four ADC channels. These are implemented using a single ADC converter which is multiplexed on to each ...
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TETRA Baseband Processor Bit Name Active State 0 StartConvert High Address and Data format for Auxillary ADC Control access Address field [6: 1999 Consumer Microcircuits Limited One-shot conversion control bit. Only valid when the ADCs are ...
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TETRA Baseband Processor AuxAdcData Title: Auxiliary ADC Data registers Address: (Eight registers) $0x10 to $0x17 Function: R Description: These registers enable the user to inspect the conversion value for each of the four auxiliary ADCs. There are two read registers ...
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TETRA Baseband Processor Bit Name Active State Address $0x17 7:0 Adc4MsbData Data Address and Data format for Auxillary ADC Data access Address field [6: ADC Channel 0 0 ...
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TETRA Baseband Processor RamDacCtrl Title: RamDac Control register Address: $0x0C Function: RW Description: This register controls the operation of DAC 1, together with the operation of the memory (DacSram) which can be used to drive the digital input of DAC ...
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TETRA Baseband Processor Address field [6: 1999 Consumer Microcircuits Limited Address and Data format for RamDacCtrl access Data field [5: CMX980A D/980A/3 ...
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TETRA Baseband Processor AuxDacData Title: Auxiliary DAC Data registers Address: (Eight registers) $0x18 to $0x1F Function: RW Description: There are two input registers for each of the four auxiliary DACs. Writing to the AuxDac#LsbData register writes the least significant two ...
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TETRA Baseband Processor Bit Name Address $0x1E 7:2 1:0 AuxDac4LsbData Address $0x1F 7:0 AuxDac4MsbData Address and Data format for Auxillary DAC Data access Address field [6: ...
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TETRA Baseband Processor LoopBackCtrl Title: LoopBack Control register Address: $0x0D Function: RW Description: This register is only used for test purposes. For normal operation all these bits should be inactive. Bit Name Active State 7:6 5 FirReset High 4 DigLoopBack ...
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TETRA Baseband Processor Bit Name Active State 0 TxtoRxDataPath High Address field [6: 1999 Consumer Microcircuits Limited RW When set active this bit connects the output of the Tx Gain, Phase, Ramping and Offset Adjustment block to ...
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TETRA Baseband Processor TxErrorStatus Title: Transmit Error Status register. Address: $0x0E Function: R Description: This register is the Tx Data path error status register. The TxIrqActive bit is set active when one of the other bits in this register is ...
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TETRA Baseband Processor TxErrStatMask Title: Transmit Error Status interrupt Mask register Address: $0x0F Function: RW Description: Masks interrupts in the TxErrorStatus Register. On taking N_RESET Low, these bits are set active, so masking out all possible interrupt sources. Each bit ...
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TETRA Baseband Processor RxErrorStatus Title: Receive Error Status register. Address: $0x20 Function: R Description: This register is the Rx Data path error status register. The RxIrqActive bit is set active when one of the other bits in this register is ...
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TETRA Baseband Processor RxErrorStatMask Title: Receive Error Status interrupt Mask register. Address: $0x21 Function: RW Description: Masks interrupts in the RxErrorStatus Register. On taking N_RESET Low, these bits are set active, so masking out all possible interrupt sources. Each bit ...
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TETRA Baseband Processor TxFIFOStatus Title: Transmit data FIFO Status register Address: $0x22 Function: R Description: This register is the Tx Data FIFO status register. The TxIrqActive bit is set active when one of the other bits in this register is ...
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TETRA Baseband Processor Address field [6: 1999 Consumer Microcircuits Limited Address and Data format for TxFIFOStatus access Data field [7: CMX980A D/980A/3 ...
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TETRA Baseband Processor TxFIFOStatMask Title: Transmit data FIFO Status interrupt Mask register Address: $0x23 Function: RW Description: Masks interrupts in the TxFIFOStatus Register. On taking N_RESET Low, these bits are set active, so masking out all possible interrupt sources. Each ...
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TETRA Baseband Processor SymClkPhase Title: Transmit Symbol Clock Phase adjustment register Address: $0x24 Function: RW Description: Allows phase adjustment of the internal symbol clock reference phase with respect to system time. The CMX980A symbol clock is a division of the ...
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TETRA Baseband Processor Address field [6: 1999 Consumer Microcircuits Limited Address and Data format for SymClkPhase access Data field [2: CMX980A D/980A/3 ...
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TETRA Baseband Processor CoeffRamData Title: I/O access addresses for the four user-accessible coefficient memories. Address: $0x26 to $0x2D (mapped over 8 locations) Function: RW Description: Each coefficient RAM has both MSB and LSB address ports assigned for read/write access. There ...
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TETRA Baseband Processor Bit Name Active State Address $0x2B 7:0 RxRRCCoeffMSB Data Address $0x2C 7:0 RxLowPsCoeffLSB Data Address $0x2D 7:0 RxLowPsCoeffMSB Data Address and Data format for 63-tap Tx RRC FIR Coefficient Ram IO access Address field [6: ...
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TETRA Baseband Processor Address and Data format for 63-tap Rx Low Pass FIR Coefficient Ram IO access Address field [6: (Coefficient Pointer)++ Coefficient Pointer 1999 Consumer Microcircuits Limited Coefficient Data field [15:0] 0 ...
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TETRA Baseband Processor ClkStopCtrl Title: Clock-Stop Control register Address: $0x3C Function: RW Description: Control of power down and clock operation. Bit Name Active State 7:4 3 RxIFClkStopMode High 2 Aux_ClkStopMode High 1 AutoClkStopMode High 0 RxClkStop High Address and Data ...
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TETRA Baseband Processor SramData Title: I/O access address for the auxiliary DAC1 memories. Address: $0x70 to $0x73 (mapped over 4 locations) Function: RW Description: These four address locations allow access to the bit SRAM. The contents of ...
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TETRA Baseband Processor Address and Data format for Sram Data I/O access Address field [6: Sram Address Pointer Sram Address Pointer Sram Address Pointer (Sram Address Pointer)++ 1999 Consumer Microcircuits Limited ...
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TETRA Baseband Processor TxRampUpInc Title: Transmit Ramp Up Increment registers. Address: $0x4C to $0x4D (mapped over 2 locations) Function: RW Description: The value in this register sets the scale of the Tx amplitude gain increments which occur over each sample ...
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TETRA Baseband Processor TxRampDnDec Title: Transmit Ramp Down Decrement registers. Address: $0x4E to $0x4F (mapped over 2 locations) Function: RW Description: The value in this register sets the scale of the Tx amplitude gain decrements which occur over each sample ...
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TETRA Baseband Processor TxIQGainMult Title: Transmit I and Q channel Gain Multiplier registers Address: $0x42, $0x43 , $0x48 and $0x49 (4 locations) Function: RW Description: A 2s-complement multiplication is performed on the Tx I and Q data signals, using these ...
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TETRA Baseband Processor [6:0] Address field [6:0] Address Field 1999 Consumer Microcircuits Limited Address and Data ...
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TETRA Baseband Processor TxIQOffset Title: Transmit I and Q channel Offset correction register Address: $0x44, $0x45, $0x4A, and $0x4B (4 locations) Function: RW Description: This register controls the Tx Data path signal offset. This offset is a 2s-complement value (N ...
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TETRA Baseband Processor [6:0] Address field Address and Data format for TxQOffset access [6:0] Address field ...
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TETRA Baseband Processor TxPhase Title: Transmit I and Q channel Phase correction register Address: $0x40, $0x41, $0x46, $0x47 (4 locations) Function: RW Description: This register controls the Tx Data path I and Q channel phase compensation. The phase may be ...
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TETRA Baseband Processor [6:0] Address field Address and Data format for TxQPhase access [6:0] Address field ...
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TETRA Baseband Processor TxDataAccess Title: Tx Data path Access point. Address: $0x50 to $0x53 (mapped over 4 locations) Function: RW Description: This register block allows direct access to the Tx Data path values just after the gain, phase and offset ...
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TETRA Baseband Processor [6:0] Address field [6:0] Address field 1999 Consumer Microcircuits Limited Address and Data ...
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TETRA Baseband Processor RxIQGainMult Title: Receive I and Q channel Gain Multiplier register Address: $0x30, $0x31, $0x34 and $0x35 (4 locations) Function: RW Description: A 2s-complement multiplication is performed on the magnitude of the Rx Data path signal and the ...
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TETRA Baseband Processor [6:0] Address field [6:0] Address field 1999 Consumer Microcircuits Limited Address and Data ...
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TETRA Baseband Processor RxIQOffset Title: Receive I and Q Channel Offset correction register Address: $0x32, $0x33, $0x36, and $0x37 (4 locations) Function: RW Description: This register controls the Rx Data path signal offset. This offset is a 2s-complement value (N ...
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TETRA Baseband Processor [6:0] Address field [6:0] Address field 1999 Consumer Microcircuits Limited Address and Data ...
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TETRA Baseband Processor RxDataAccess Title: Rx Data path Access point. Address: $0x38 to $0x3B (mapped over 4 locations) Function: RW Description: This register block allows direct access to the Rx Data path values just after the Rx gain and offset ...
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TETRA Baseband Processor BISTControl Title: Built In Self Test Control register Address: $0x62 Function: RW Description: This register block allows control of BIST operations. Bit Name 7 TestCompleteAck 6 n_RampDelayEn 5 BISTDataRateHi 4 BISTEn 3 ContinuousBIST 2 EnRxDigitalFeedBack High 1 ...
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TETRA Baseband Processor BISTPRSG Title: Built In Self Test Pseudo Random Sequence Generator Address: $0x60 to $0x61 (2 locations) Function: RW Description: This register block allows control of BIST operations. This 16-bit number controls the length of the BIST data ...
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TETRA Baseband Processor BISTCRCRegisters Title: Built In Self Test Cyclic Redundancy Code checking Registers Address: $0x64 to $0x6D (10 locations) Function: R Description: This register block allows BIST CRC checksums to be read. Bit Name Active State Address $0x64 7:0 ...
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TETRA Baseband Processor Address and Data format for 79-tap I channel CRC register access [6:0] Address field Address and Data format for 79-tap Q channel CRC ...
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TETRA Baseband Processor PAGE 1 ADDRESSED REGISTERS DirectWrite79tapI Title: Direct write access to 79-tap I channel filter Address: $0x20 - $0x2F (16 locations) Function: RW Description: These registers are the direct access points to the 79-tap filter I channel. Writing ...
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TETRA Baseband Processor Address and Data format for 79-tap filter I channel Direct Write “Write” access Address field [6: D11 Address and Data format for 79-tap I channel filter Direct Write “Read” access LSB data access Address ...
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TETRA Baseband Processor DirectWrite79tapQ Title: Direct write access to 79 tap Q channel filter Address: $0x10 - $0x1F (16 locations) Function: RW Description: These registers are the direct access points to the 79-tap filter Q channel. Writing accesses the holding ...
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TETRA Baseband Processor Address and Data format for 79-tap filter Q channel Direct Write “Write” access Address field [6: D11 Address and Data format for 79-tap Q channel filter Direct Write “Read” access LSB data access Address ...
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TETRA Baseband Processor 1.6 Application Notes 1.6.1 Interrupt Handling Interrupt handling requires an extra read to clear the source of the interrupt. Handling interrupts is sometimes a source of confusion. The notes below are intended to clarify the operation of ...
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TETRA Baseband Processor (R3/C3 for Tx, R2/C2 for Rx, as shown in Figures 2a and b) are also scaled with MCLK. For the case of MCLK = 8.192MHz, this means increasing the RC products by approximately 10%. There is a ...
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TETRA Baseband Processor there are additional sources of attenuation or phase distortion, these can be catered for either by designing a new pre-emphasis filter which incorporates gain to compensate for the attenuation in the above table designing another ...
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TETRA Baseband Processor 1.6.4.3 General Procedure for Reconfiguring the CMX980A FIR Filters 1. Obtain or design the required filter characteristic(s), either z-transform format. Note that all programmable FIR filters are sampled at a frequency of MCLK/64. This ...
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TETRA Baseband Processor 1.6.7 Receiver Re-Synchronisation /* Pseudo-code for the use of re-synchronising feature in the CMX980A */ /* /* When using low data rate on the rx data serial port /* alternate I & Q samples are transmitted. /* ...
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TETRA Baseband Processor 1.6.8 Guidelines for use of Power Save Modes The CMX980A contains a number of power save modes. In order to maximise flexibility for different architectures and modes of operation, several register bits are available which control different ...
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TETRA Baseband Processor 1.6.8.5 Serial Interface Section A small power saving can be made possible to run with a serial interface clock rate of MCLK/8. This is accomplished by setting the DataRateHi bit in the ConfigCtrl1 Register ...
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TETRA Baseband Processor 1.7 Performance Specification 1.7.1 Electrical Performance 1.7.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Supply CC1 SS1 CC2 SS2 ...
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TETRA Baseband Processor 1.7.1.3 Operating Characteristics Details in this section represent design target values and are not currently guaranteed. For the following conditions unless otherwise specified: MCLK Frequency = 9.216MHz, Symbol Rate = 18k bits/sec, selected when Rx enabled. (V ...
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TETRA Baseband Processor Notes: 1. Not including any current drawn from the device pins by external circuitry. 2. Timing for an external input to the MCLK pin. General Points: 3. The current quoted when MCLK is not toggled is essentially ...
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TETRA Baseband Processor Transmit Parameters Parameter Input bit rate (2 bits per symbol) Number of Channels Modulation Type FIR filter sampling rate DAC output update rate DAC resolution Integral accuracy Differential accuracy Signal to noise plus distortion Offset (without adjustment) ...
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TETRA Baseband Processor Parameter TETRA Specific Parameters (continued) Adjacent Channel Power during ramping over 5 symbols at 25kHz frequency offset Linear Ramping Sigmoidal Ramping Vector Error (peak) Tx Notes: 1. Measured with an MCLK/4096 test signal in MCLK/1024 bandwidth 2. ...
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TETRA Baseband Processor Receive Parameters Parameter Input impedance (Capacitive load to V Input impedance (Source impedance should be < Differential Input voltage (V CC Signal to Noise Signal to Noise plus distortion rd 3 order intercept (3.3V operation) ...
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TETRA Baseband Processor Rx Notes: 1. Note this means 0.85V or 0.56V on each input of the differential pair. 2. Both measured with MCLK/4096 Hz test signal, in MCLK/1024 Hz bandwidth. 3. Extrapolated from third harmonic distortion at maximum signal. ...
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TETRA Baseband Processor Auxiliary Circuit Parameters Parameter DACs Resolution Settling time to 0.5 LSB Output resistance Integral non-linearity Differential non-linearity Zero error (offset) Power (all DACs operating) Resistive Load Output noise voltage in 30kHz bandwidth ADC and Multiplexed inputs Input ...
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TETRA Baseband Processor 1.7.1.3 Operating Characteristics - Timing Diagrams The following timings are provisional: Timing Parameters - Serial Ports MCLK to SClk out - low to high MCLK to SClk out - high to low CmdDat setup to falling edge ...
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TETRA Baseband Processor 1999 Consumer Microcircuits Limited Figure 5a Basic Serial Port Signals 101 CMX980A D/980A/3 ...
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TETRA Baseband Processor 1999 Consumer Microcircuits Limited Figure 5b Command Write operation 102 CMX980A D/980A/3 ...
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TETRA Baseband Processor 1999 Consumer Microcircuits Limited Figure 5c Bi-dir Command Read Operation 103 CMX980A D/980A/3 ...
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TETRA Baseband Processor Figure 5d Non bi-dir Command Read Operation 1999 Consumer Microcircuits Limited 104 CMX980A D/980A/3 ...
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TETRA Baseband Processor 1999 Consumer Microcircuits Limited Figure 5e Rx Data Serial Port Read Operation 105 CMX980A D/980A/3 ...
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... TETRA Baseband Processor 1.7.2 Packaging Figure 6 L6 Mechanical Outline: Order as part no. CMX980AL6 Figure 7 L7 Mechanical Outline: Order as part no. CMX980AL7 1999 Consumer Microcircuits Limited 106 CMX980A D/980A/3 ...
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Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. ...
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... In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title circuits ...