TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 593
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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18.6.7
31-8
7-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
Host Controller Driver determines the alignment restrictions by writing all 1s to HcHCCA and reading the con-
tent of HcHCCA. The alignment is evaluated by examining the number of zeroes in the lower order bits. The
minimum alignment is 256 bytes; therefore, bits 0 through 7 must always return "0" when read. This area is
used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and
the Host Controller Driver.
HCCA[23:0]
−
The HcHCCA register contains the physical address of the Host Controller Communication Area. The
Bit Symbol
HcHCCA Register
31
23
15
0
0
0
7
-
R/W
−
(HCD)
Type
30
22
14
0
0
0
6
R
−
-
Type
(HC)
Filed name:Host Controller Communication Area
This is the base address of the Host Controller Communication Area.
Reserved
29
21
13
0
0
0
5
-
Page 567
28
20
12
0
0
0
4
-
HCCA
HCCA
HCCA
27
19
11
0
0
0
3
-
Function
26
18
10
0
0
0
2
-
25
17
0
0
9
0
1
-
TMPM363F10FG
24
16
0
0
8
0
0
-
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