TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 398
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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12.16
Operation in Each Mode
Figure 12-17 Transmit / Receive Operation in the I/O Interface Mode (SCLK Input Mode)
SCLK input
SCLK input
SCLK input
TXD
RXD
PERR (Underrun error)
Receive data
read timing
Transmit data
write timign
TXD
RXD
(INTTXx interrupt
(INTRXx interrupt
Receive data
read timing
Transmit data
write timign
TXD
RXD
(INTTXx interrupt
(INTRXx interrupt
Receive data
read timing
Transmit data
write timign
(INTTXx interrupt
(INTRXx interrupt
request)
request)
request)
request)
request)
request)
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
<WBUF> = "1" (if double buffering is enabled with no errors)
<WBUF> = "1" (if double buffering is enabled with error generation)
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
<WBUF> = "0" (if double buffering is disabled)
Page 372
bit 5
bit 5
bit 5
bit 5
bit 5
bit 5
bit 6
bit 6
bit 6
bit 6
bit 6
bit 6
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
A
A
A
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
TMPM363F10FG
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
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