TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 296
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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Manufacturer
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Price
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10.3
Description of Registers
10.3.9
31-20
19-17
16-14
13-11
10-8
7-4
3-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
−
t_tr[2:0]
−
t_wp[2:0]
t_ceoe[2:0]
t_wc[3:0]
t_rc[3:0]
Bit Symbol
smc_sram_cycles0_2 (SMC SRAM Cycles Registers 0 <2>)
Undefined
Undefined
31
23
15
1
7
1
-
-
-
W
R
R
R
R
R
R
Type
Undefined
Undefined
30
22
14
0
6
1
-
-
-
Write as "0".
Turn around cycle time
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
Read as undefined.
WE pulse cycle time
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
Delay cycle time to OE assert
001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock
Write cycle time
0011 to 1111 : SMCCLK × 3 clock to SMCCLK × 15 clock
Read cycle time
0010 to 1111 : SMCCLK × 2 clock to SMCCLK × 15 clock
t_wc
Undefined
Undefined
29
21
13
1
5
0
-
-
Page 270
Undefined
Undefined
t_wp
28
20
12
1
4
0
-
-
Undefined
27
19
11
Function
0
0
3
1
-
Undefined
t_tr
26
18
10
0
0
2
1
-
t_rc
Undefined
t_ceoe
25
17
1
9
1
1
0
-
TMPM363F10FG
Undefined
24
16
0
8
1
0
0
-
-
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