TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 588
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TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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18.6
Register
18.6.3
troller Driver, as well as reflecting the current status of the Host Controller. To the Host Controller Driver, it
appears to be a "write to set" register. The Host Controller must ensure that bits written as "1" are set in the reg-
ister while bits written as "0" remain unchanged in the register. The Host Controller Driver may issue multi-
ple distinct commands to the Host Controller without concern for corrupting previously issued commands.
The Host Controller Driver has normal read access to all bits.
ted the scheduling overrun error. This occurs when the Periodic list does not complete before EOF. When a
scheduling overrun error is detected, the Host Controller increments the counter and sets the SchedulingOver-
run field in the HcInterruptStatus register.
The HcCommandStatus register is used by the Host Controller to receive commands issued by the Host Con-
The SchedulingOverrunCount field indicates the number of frames with which the Host Controller has detec-
HcCommandStatus Register
Page 562
TMPM363F10FG
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