TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 387

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

12.15
12.14.3
12.14.3.1
12.14.3.2
SCxMOD0<RXE>, SCxMOD1<TXE>, SCxMOD2<TBEMP><RBFLL><TXRUN>, SCxCR<OERR><PERR>
<FERR> are initialized. And the receive circuit, the transmit circuit and the FIFO become initial state. Other
states are maintained.
Software reset is generated by writing SCxMOD2<SWRST[1:0]> as "10" followed by "01". As a result,
Software Reset
Error Generation
Note:Over-run error and Under-run error have no meaning in SCLK output mode.
Overrun error
Underrun error
UART Mode
I/O Interface Mode
Framing error
Overrun error
Parity Error
Modes
Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
Immediately after the rising or falling edge of the next SCLK.
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
Page 361
9 bits
−
Around the center of stop bit
Around center of parity bit
7 bits + parity
8bits + parity
7 bits
8 bits
TMPM363F10FG