TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 394

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

12.16
Operation in Each Mode
Figure 12-15 Receive Operation in the I/O Interface Mode (SCLK Input Mode)
SCLK input
(<SCLKS>=”0”
RBFLL
SCLK input
(<SCLKS>=”0”
Receive data
read timing
SCLK input
(<SCLKS>=”1”
RXD
(INTRXx interrupt
Receive data
read timing
SCLK input
(<SCLKS>=”1”
RXD
(INTRXx interrupt
RBFLL
OERR
Rising mode)
Rising mode)
falling mode)
request)
falling mode)
request)
(2)
be moved to the receive buffer from the shift register, and the receive buffer can receive the next
frame successively.
In the SCLK input mode, receiving double buffering is always enabled, the received frame can
The INTRXx receive interrupt is generated each time received data is moved to the receive buffer.
SCLK Input Mode
bit 0
bit 0
If data is read from buffer
If data can not be read from buffer
bit 1
bit 1
Page 368
bit 5
bit 5
bit 6
bit 6
bit 7
bit 7
TMPM363F10FG
bit 0
bit 0