TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 464

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

14.8
Control in SIO mode
INTSBIx
interrupt request
14.8.2.2
<SIOS>
<SIOF>
<SEF>
SCKx pin(Output)
SIx pin
SBIxDBR
INTSBIx interrupt
SBIxCR1
SBIxCR1
Reg.
ta is taken into the shift register from the SI pin, with the least-significant bit (LSB) first, in synchroniza-
tion with the serial clock. Once the shift register is loaded with the 8-bit data, it transfers the received da-
ta to SBIxDBR and the INTSBIx (buffer-full) interrupt request is generated to request reading the re-
ceived data. The interrupt service program then reads the received data from SBIxDBR.
the received data is read from SBIxDBR.
The maximum data transfer rate varies, depending on the maximum latency between generating the inter-
rupt request and reading the received data
terrupt service program. If <SIOS> is cleared, reception continues until all the bits of received data are writ-
ten to SBIxDBR. The program checks SBIxSR<SIOF> to determine whether reception has come to an
end.<SIOF> is cleared to "0" at the end of reception. After confirming the completion of the reception,
last received data is read. If <SIOINH> is set to "1", the reception is aborted immediately and <SIOF> is
cleared to "0". (The received data becomes invalid, and there is no need to read it out.)
Set the control register to the receive mode. Then writing "1" to SBIxCR1<SIOS> enables reception.Da-
In the internal clock mode, the serial clock will be stopped and automatically be in the wait state until
In the external clock mode, shift operations are executed in synchronization with the external clock.
Reception can be terminated by clearing <SIOS> to "0" or setting <SIOINH> to "1" in the INTSBIx in-
Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongo-
8-bit receive mode
ing reception must be completed by clearing <SIOS> to "0" and the last received data must
be read before the transfer mode is changed.
←
←
←
Figure 14-19 Receive Mode (Example: Internal Clock)
7
0
1
SBIxDBR
a
0
6
1
0
a
5
1
1
1
a
4
1
1
2
3
0
0
a
3
2
X
X
a
4
1
X
X
Page 438
a
5
0
X
X
a
6
Read receive data
a
Selects the receive mode.
Starts reception.
Reads the received data.
7
a
b
0
b
1
b
2
Clear <SIOS>
b
3
b
4
b
5
TMPM363F10FG
b
6
Read receive data
b
7
b