TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 537

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.5
16.5.1
Operation explain of each circuit
CPU controls the CAN controller by changing the settings of the mailboxes and control registers. The set-
tings of the mailboxes and control registers are used for such processes as reception filtering, message transmis-
sion, and interrupt processing.
ter the bit has been set, all transmission procedures and error processes (when errors occur) are executed with-
out CPU involvement. When the mailbox is set to receive, the CPU reads the mailbox data using read instruc-
tions. The user can also set it so that an interrupt will be issued to the CPU every time a message has been suc-
cessfully received or transmitted
bits. The mailboxes (except mailbox 31) can be set to either transmission or reception. Mailbox 31 is the re-
ceive-only mailbox. Mailbox 31 is designed so that it can receive different message ID groups using other re-
ceive masks than mailboxes 0 to 30.
The mailboxes consist of a single port RAM (accessible from the internal CAN core and the CPU). The
To start transmission, set the transmit request bit corresponding to the mailbox to transmit messages to. Af-
In total, 32 mailboxes are provided, each of which consists of 8 byte data, 29 bit IDs, and several control
Figure 16-2 shows the configuration of the mailboxes.
Mailbox
1. Message ID field (ID3 to ID0)
2. Message control field (MCF)
3. Time stamp value (TSV1, TSV0)
4. Data field (D7 to D0)
MailBox
(CANMBx (x=0~31))
・ ID extension bit <IDE>
・ Global / local acceptance mask enable bit <GAME / LAME>
・ Remote frame handling bit <RFH>
・ 29-bit message ID <ID[28:0]>
・ Remote frame transmit request bit <RTR>
・ Data length of 4 bits <DLC[3:0]>
Stores time stamp counter value during receiving / transmitting message. (TSV[15:0]>
Data of 8 bytes <D7[7:0]> to <D0[7:0]>
Figure 16-2 Configuration of Mailboxes
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31
TSV1
Byte3
ID3
D7
D3
HalfWord1
24
23
TSV0
Byte2
ID2
D6
D2
16
Word
15
ID1
Byte1
D5
D1
HalfWord0
8
7
MCF
Byte0
ID0
D4
D0
0
0x0018
0x0010
0x0008
0x0000
Offset Address
TMPM363F10FG