TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 23

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

24. Flash
23.4 Operational Description.......................................................................................................661
23.5 Alarm function.....................................................................................................................664
24.1 Flash Memory......................................................................................................................667
24.2 Operation Mode...................................................................................................................670
24.3 On-board Programming of Flash Memory (Rewrite/Erase)...............................................708
23.3.2
23.3.3
23.4.1
23.4.2
23.4.3
23.5.1
23.5.2
23.5.3
24.1.1
24.1.2
24.2.1
24.2.2
24.2.3
24.2.4
24.2.5
24.2.6
24.2.7
24.2.8
24.2.9
24.2.10
24.2.11
24.3.1
24.3.2
23.3.3.1
23.3.3.2
23.3.3.3
23.3.3.4
23.3.3.5
23.3.3.6
23.3.3.7
23.3.3.8
23.3.3.9
23.3.3.10
23.3.3.11
24.2.2.1
24.2.2.2
24.2.3.1
24.2.9.1
24.2.9.2
24.2.9.3
24.2.9.4
24.2.10.1
24.2.10.2
24.2.10.3
24.2.10.4
24.2.10.5
24.2.10.6
24.2.10.7
24.2.10.8
24.2.10.9
24.3.1.1
24.3.1.2
24.3.1.3
24.3.1.4
24.3.1.5
24.3.1.6
24.3.2.1
Control Register.............................................................................................................................................................652
Detailed Description of Control Register.....................................................................................................................654
Reading clock data........................................................................................................................................................661
Writing clock data.........................................................................................................................................................661
Entering the Low Power Consumption Mode..............................................................................................................663
1Hz cycle "Low" pulse..................................................................................................................................................665
16Hz cycle "Low" pulse................................................................................................................................................665
Features..........................................................................................................................................................................667
Block Diagram of the Flash Memory Section..............................................................................................................669
Reset Operation.............................................................................................................................................................671
User Boot Mode (Single chip mode)............................................................................................................................671
Single Boot Mode..........................................................................................................................................................680
Configuration for Single Boot Mode............................................................................................................................683
Memory Map.................................................................................................................................................................683
Interface specification....................................................................................................................................................685
Data Transfer Format....................................................................................................................................................686
Restrictions on internal memories.................................................................................................................................686
Transfer Format for Boot Program...............................................................................................................................686
Flash Memory................................................................................................................................................................708
Address bit configuration for bus write cycles.............................................................................................................718
"Low" pulse (when the alarm register corresponds with the clock)...........................................................................664
Operation of Boot Program.........................................................................................................................................693
General Boot Program Flowchart...............................................................................................................................707
RTCSECR (Second column register (for PAGE0 only))
RTCMINR (Minute column register (PAGE0/1))
RTCHOURR (Hour column register(PAGE0/1))
RTCDAYR (Day of the week column register(PAGE0/1))
RTCDATER (Day column register (for PAGE0/1 only))
RTCMONTHR (Month column register (for PAGE0 only))
RTCMONTHR (Selection of 24-hour clock or 12-hour clock (for PAGE1 only))
RTCYEARR (Year column register (for PAGE0 only))
RTCYEARR (Leap year register (for PAGE1 only))
(1-A) Method 1: Storing a Programming Routine in the Flash Memory
(1-B) Method 2: Transferring a Programming Routine from an External Host
(2-A) Using the Program in the On-Chip Boot ROM
RAM Transfer
Show Flash Memory SUM
Transfer Format for the Show Product Information
Chip Erase and Protect Bit Erase
Block Configuration
Basic Operation
Reset (Hardware reset)
Commands
Flash control / status register
List of Command Sequences
Flowchart
RTCPAGER(PAGE register(PAGE0/1))
RTCRESTR (Reset register (for PAGE0/1))
RAM Transfer Command
Show Flash Memory SUM Command
Show Product Information Command
Chip and Protection Bit Erase Command
Acknowledge Responses
Determination of a Serial Operation Mode
Password
Calculation of the Show Flash Memory Sum Command
Checksum Calculation
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