TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 108
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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7.6
Exception / Interrupt-Related Registers
31
30-16
15-8
7-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
7.6.2.5
Bit
−
SETENA
−
SETENA
Bit Symbol
(Interrupt 23)
(Interrupt 7)
SETENA
SETENA
Interrupt Set-Enable Register 1
Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources".
31
23
15
0
0
0
7
0
-
-
R/W
R/W
R/W
R/W
Type
(Interrupt 30)
(Interrupt 22)
(Interrupt 6)
SETENA
SETENA
SETENA
30
22
14
0
0
0
6
0
-
Write as 0.
Interrupt number [30:16]
[Write]
1: Enable
[Read]
0: Disabled
1: Enabled
Each bit corresponds to the specified number of interrupts.
Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect.
Reading the bits can see the enable/disable condition of the corresponding interrupts.
Write as 0.
Interrupt number [7:0]
[Write]
1: Enable
[Read]
0: Disabled
1: Enabled
Each bit corresponds to the specified number of interrupts.
Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect.
Reading the bits can see the enable/disable condition of the corresponding interrupts.
(Interrupt 29)
(Interrupt 21)
(Interrupt 5)
SETENA
SETENA
SETENA
29
21
13
0
0
0
5
0
-
(Interrupt 28)
(Interrupt 20)
(Interrupt 4)
Page 82
SETENA
SETENA
SETENA
28
20
12
0
0
0
4
0
-
(Interrupt 27)
(Interrupt 19)
(Interrupt 3)
SETENA
SETENA
SETENA
27
19
11
Function
0
0
0
3
0
-
(Interrupt 26)
(Interrupt 18)
(Interrupt 2)
SETENA
SETENA
SETENA
26
18
10
0
0
0
2
0
-
(Interrupt 25)
(Interrupt 17)
(Interrupt 1)
SETENA
SETENA
SETENA
25
17
0
0
9
0
1
0
-
TMPM363F10FG
(Interrupt 24)
(Interrupt 16)
(Interrupt 0)
SETENA
SETENA
SETENA
24
16
0
0
8
0
0
0
-
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