SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 815

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

44.3.7.3
44.3.7.4
44.3.8
44.3.8.1
44.3.9
44.3.9.1
44.3.10
44.3.10.1
6384E–ATARM–05-Feb-10
Shutdown Controller (SHDWC)
Static Memory Controller (SMC)
System Controller (SYSC)
SSC: Transmitter Limitations in Slave Mode
SSC: Periodic Transmission Limitations in Master Mode
SMC: Chip Select Parameters Modification
SYSC: Possible Event Loss when reading RTT_SR
SHDWC: SHDN Signal may be Driven to Low Level Voltage During Device Power-on
None.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
None.
If Last Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent.
None.
If only VDDBU is powered during boot sequence (No VDDCORE), the SHDN signal may be
driven to low level voltage after a delay.This delay is linked to the startup time of the slow clock
selected by OSCSEL signal.
If SHDN pin is connected to the Enable pin (EN) of the VDDCORE regulator, VDDCORE estab-
lishment does not occur and the system does not start.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code
from a memory connected on this CS0, may lead to unpredictable behavior.
The code used to modify the parameters of an SMC Chip Select can be executed from the inter-
nal RAM or from a memory connected to another Chip Select
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is
read, the corresponding bit might be cleared. This can lead to the loss of this event.
The software must handle an RTT event as an interrupt and should not poll RTT_SR.
1. VDDCORE must be established within the delay corresponding to the startup time of
2. Add a glue logic to latch the rising edge of the SHDN signal. The reset of the latch out-
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
the slow clock selected by OSCSEL.
put (EN_REG) can be connected to a PIO and used to enter the shutdown mode.
AT91SAM9G20
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