SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 323
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
- Current page: 323 of 832
- Download datasheet (13Mb)
6384E–ATARM–05-Feb-10
When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:
Note:
Note:
1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are
2. The instruction at the ARM interrupt exception vector address is required to work with
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in
2. The ARM core enters Interrupt mode, if it has not already done so.
3. When the instruction loaded at address 0x18 is executed, the program counter is
4. The previous step has the effect of branching to the corresponding interrupt service
5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-
6. The interrupt handler can then proceed as required, saving the registers that will be
7. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that
8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indi-
LDR PC, [PC, # -&F20]
loaded with corresponding interrupt service routine addresses and interrupts are
enabled.
the vectoring
the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18.
In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, dec-
rementing it by four.
loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects:
– Sets the current interrupt to be the pending and enabled interrupt with the highest
– De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR
– Automatically clears the interrupt, if it has been programmed to be edge-triggered.
– Pushes the current level and the current interrupt number on to the stack.
– Returns the value written in the AIC_SVR corresponding to the current interrupt.
routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link
register must be decremented by four when it is saved if it is to be restored directly into
the program counter at the end of the interrupt. For example, the instruction SUB PC,
LR, #4 may be used.
assertion of the nIRQ to be taken into account by the core. This can happen if an inter-
rupt with a higher priority than the current interrupt occurs.
used and restoring them at the end. During this phase, an interrupt of higher priority
than the current level will restart the sequence from step 1.
the interrupt is completed in an orderly manner.
cate to the AIC that the current interrupt is finished. This causes the current level to be
popped from the stack, restoring the previous current level if one exists on the stack. If
another interrupt is pending, with lower or equal priority than the old current level but
with higher priority than the new current level, the nIRQ line is re-asserted, but the inter-
rupt sequence does not immediately start because the “I” bit is set in the core.
SPSR_irq is restored. Finally, the saved value of the link register is restored directly into
the PC. This has the effect of returning from the interrupt to whatever was being exe-
cuted before, and of loading the CPSR with the stored SPSR, masking or unmasking
the interrupts depending on the state saved in SPSR_irq.
priority. The current level is the priority level of the current interrupt.
must be read in order to de-assert nIRQ.
If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared dur-
ing this phase.
The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of
masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored,
the mask instruction is completed (interrupt is masked).
AT91SAM9G20
323
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