SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 596

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

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AT91SAM9G20
The two bus modes (open drain and push/pull) needed to process all the operations are defined
in the MCI command register. The MCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:
Table 35-4.
The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register
are described in
Table 35-5.
Note:
Table 35-6.
The MCI_ARGR contains the argument field of the command.
To send a command, the user must perform the following steps:
The command is sent immediately after writing the command register. The status bit CMDRDY
in the status register (MCI_SR) is asserted when the command is completed. If the command
requires a response, it can be read in the MCI response register (MCI_RSPR). The response
size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error
detection to prevent any corrupted data during the transfer.
The following flowchart shows how to send a command to the card and read the response if
needed. In this example, the status register bits are polled but setting the appropriate bits in the
interrupt enable register (MCI_IER) allows using an interrupt method.
CMD
CMD Index
CMD2
Field
CMDNB (command number)
RSPTYP (response type)
SPCMD (special command)
OPCMD (open drain command)
MAXLAT (max latency for command to response)
TRCMD (transfer command)
TRDIR (transfer direction)
TRTYP (transfer type)
IOSPCMD (SDIO special command)
• Fill the argument register (MCI_ARGR) with the command argument.
• Set the command register (MCI_CMDR) (see
bcr means broadcast command with response.
S
T
ALL_SEND_CID Command Description
Fields and Values for MCI_CMDR Command Register
Type
bcr
Table 35-5
Host Command
Content
Argument
[31:0] stuff bits
and
CRC
Table
E
35-6.
Z
N
Resp
R2
ID
******
Cycles
Table
2 (CMD2)
0 (No transfer)
X (available only in transfer command)
X (available only in transfer command)
Value
2 (R2: 136 bits response)
0 (not a special command)
1
0 (NID cycles ==> 5 cycles)
0 (not a special command)
Abbreviation
ALL_SEND_CID
Z
35-6).
S
T
Content
CID
Command
Description
Asks all cards to send
their CID numbers on
the CMD line
6384E–ATARM–05-Feb-10
Z
Z
Z