SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 422

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 31-6. Master Write with On Data Byte
Figure 31-7. Master Write with Multiple Data Byte
Figure 31-8. Master Write with One Byte Internal Address and Multiple Data Bytes
31.7.5
422
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
Write THR (Data n)
AT91SAM9G20
Master Receiver Mode
S
Write THR (Data n)
S
DADR
TXCOMP
DADR
TXRDY
TWD
When no more data is written into the TWI_THR, the master generates a stop condition to end
the transfer. The end of the complete transfer is marked by the TWI_TXCOMP bit set to one.
See
TXRDY is used as Transmit Ready for the PDC transmit channel.
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
W
Write THR (DATA)
S
Figure
W
A
31-6,
DADR
IADR(7:0)
A
Figure
Write THR (Data n+1)
DATA n
W
31-7, and
A
A
DATA n
Write THR (Data n+1)
A
Figure
DATA
31-8.
A
Write THR (Data n+x)
DATA n+5
Last data sent
(ACK received and TXRDY = 1)
A
STOP sent automaticaly
Write THR (Data n+x)
DATA n+5
Last data sent
P
A
A
DATA n+x
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
STOP sent automaticaly
DATA n+x
STOP sent automaticaly
6384E–ATARM–05-Feb-10
A
A
P
P