SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 306
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
- Current page: 306 of 832
- Download datasheet (13Mb)
26.9.10
Register Name:CKGR_PLLBR
Access Type:Read-write
Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC.
• DIVB: Divider B
• PLLBCOUNT: PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• OUTB: PLL B Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MULB: PLL B Multiplier
0 = The PLL B is deactivated.
1 up to 62 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1.
• USBDIV: Divider for USB Clock.
306
DIVB
0
1
2 - 255
0
0
1
1
31
23
15
–
–
7
AT91SAM9G20
PMC Clock Generator PLL B Register
OUTB
USBDIV
0
1
0
1
30
22
14
–
–
6
29
21
13
5
USBDIV
Divider Selected
Divider output is PLL B clock output
Divider output is PLL B clock output divided by 2
Divider output is PLL B clock output divided by 4
Reserved
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIVB.
28
20
12
4
DIVB
27
19
11
–
3
PLLBCOUNT
MULB
26
18
10
–
2
25
17
–
9
1
6384E–ATARM–05-Feb-10
24
16
–
8
0
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