SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 780

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.9.2
780
AT91SAM9G20
Write Timings
Table 41-27. SMC Read Signals - NCS Controlled (READ_MODE= 0) (Continued)
Table 41-28. SMC Write Signals - NWE controlled (WRITE_MODE = 1)
Note:
SMC
SMC
SMC
SMC
SMC
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
10
11
12
13
14
15
16
17
18
19
20
21
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr
hold length” or “NWE hold length”.
Parameter
Data Out Valid before NWE High
NWE Pulse Width
NBS0/A0 NBS1, NBS2/A1, NBS3, A2
- A25 valid before NWE low
NCS low before NWE high
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2 - A25
change
NWE High to NCS Inactive
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2 - A25,
NCS change
Data Setup before NCS High
Data Hold after NCS High
A2 - A25 valid before NCS High
NRD low before NCS High
NCS Pulse Width
NBS0/A0, NBS1, NBS2/A1, NBS3,
HOLD or NO HOLD SETTINGS (ncs rd hold ≠ 0, ncs rd hold = 0)
HOLD or NO HOLD SETTINGS (nwe hold ≠ 0, nwe hold = 0)
(1)
NO HOLD SETTINGS (nwe hold = 0)
HOLD SETTINGS (ncs rd hold ≠ 0)
HOLD SETTINGS (nwe hold ≠ 0)
(1)
nwe hold * t
wr hold)* t
(nwe setup - ncs
length * t
pulse) * t
(nwe hold - ncs
(ncs rd setup +
(ncs rd setup +
rd setup + nwe
ncs rd pulse)*
ncs rd pulse -
1.8V Supply
ncs rd pulse
nwe pulse *
nwe pulse *
nwe setup *
nrd setup)*
t
t
t
t
t
CPMCK
CPMCK
CPMCK
CPMCK
CPMCK
-0.4
0.2
0.3
3.4
9.2
0.1
0
CPMCK
CPMCK
-0.8
-0.4
-0.5
CPMCK
-0.8
-0.2
CPMCK
+
-
Min
-
length * t
(nwe setup - ncs
(ncs rd setup +
(ncs rd setup +
pulse) * t
wr hold)* t
(nwe hold - ncs
ncs rd pulse)*
ncs rd pulse -
rd setup + nwe
ncs rd pulse
3.3V Supply
nrd setup)*
t
t
nwe pulse *
nwe pulse *
nwe setup *
t
t
t
t
CPMCK
CPMCK
nwe hold *
CPMCK
CPMCK
CPMCK
CPMCK
7.6
0.1
-0.3
0.2
3.1
0
6384E–ATARM–05-Feb-10
CPMCK
-0.6
-0.3
CPMCK
-0.8
-0.4
-0.5
-0.4
CPMCK
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns