SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 776

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.8
Table 41-24. Power-On-Reset Characteristics
41.8.1
41.8.2
776
Symbol
V
V
T
RES
th+
th-
Core Power Supply POR Characteristics
AT91SAM9G20
Power Sequence Requirements
Power-up Sequence
Parameter
Threshold Voltage Rising
Threshold Voltage Falling
Reset Time
The AT91SAM9G20 board design must comply with the power-up and power-down sequence
guidelines below to guarantee reliable operation of the device. Any deviation from these
sequences may lead to the following situations:
The power sequence described below is applicable to all the AT91SAM9G20 revisions. How-
ever, the power sequence can be simplified for the revision B device. In this revision, the over
consumption during the power-up phase has been limited to less than 200 mA. This current can
not damage the device and if it is acceptable for the final application, the power sequence
becomes VDDIO followed by VDDCORE. VDDIO must be established first (>0.7V) to ensure a
correct sampling of the BMS signal and also to guarantee the correct voltage level when access-
ing an external memory.
Figure 41-2. VDDCORE and VDDIO Constraints at Startup
• Excessive current consumption during the power-up phase which, in the worst case, can
• Prevent the device from booting.
result in irreversible damage to the device.
VDDCOREtyp
V th+ (0.5V)
Core Supply POR output
V oh (2.6V)
VDDIOtyp
VDD (V)
SLCK
0.7V
Conditions
Minimum Slope of +1.0V/100ms
<--------------------- T1--------------------->
<T2>
<T3>
<-------------T4----------->
Min
0.5
0.4
30
Typ
0.7
0.6
70
VDDIO > V oh
VDDCORE
6384E–ATARM–05-Feb-10
VDDIO
Max
0.89
0.85
130
t
Units
µs
V
V