SAM9G20 Atmel Corporation, SAM9G20 Datasheet
SAM9G20
Specifications of SAM9G20
Related parts for SAM9G20
SAM9G20 Summary of contents
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... Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected • Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention ® ® ARM Thumb Processor ® Technology for Java ® Acceleration AT91 ARM Thumb Microcontrollers AT91SAM9G20 6384E–ATARM–05-Feb-10 ...
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... VDDIOP (Peripheral I/Os) – 3.0V to 3.6V for VDDUSB – 3.0V to 3.6V VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in a 217-ball LFBGA and 247-ball TFBGA RoHS-compliant Package AT91SAM9G20 2 ™ Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding 6384E–ATARM–05-Feb-10 ...
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... The AT91SAM9G20 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a USB Host control- ler. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface ...
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... AT91SAM9G20 Block Diagram Figure 2-1. AT91SAM9G20 Block Diagram AT91SAM9G20 4 Filter Filter 6384E–ATARM–05-Feb-10 ...
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... Output Input Output Input Output Shutdown, Wakeup Logic Output Input ICE and JTAG Input Input Input Output Input Input Output AT91SAM9G20 Active Level Comments 1.65V to 1.95V or 3.0V to 3.6V 1.65V to 3.6V 0.9V to 1.1V 3.0V to 3.6V 0.9V to 1.1V 1.65V to 3.6V 0.9V to 1.1V 1.65V to 3.6V Accepts between 0V and VDDBU. Accepts between 0V and VDDBU. ...
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... CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read CFIOW CompactFlash IO Write CFRNW CompactFlash Read Not Write CFCS0 - CFCS1 CompactFlash Chip Select Lines AT91SAM9G20 6 Type Reset/Test I/O Input Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input ...
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... Output SDRAM Controller Output Output Output Output Output Output Output Multimedia Card Interface MCI Output I/O I/O I/O I/O I/O I/O Input Output Input Output Input Input Input Synchronous Serial Controller - SSC Output Input I/O I/O I/O I/O AT91SAM9G20 Active Level Comments Low Low Low Low Low High Low Low Low 7 ...
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... Transmit Coding Error ERXDV Receive Data Valid ERX0-ERX3 Receive Data ERXER Receive Error ECRS Carrier Sense and Data Valid ECOL Collision Detect EMDC Management Data Clock EMDIO Management Data Input/Output AT91SAM9G20 8 Type Timer/Counter - TCx Input I/O I/O Serial Peripheral Interface - SPIx_ I/O I/O I/O I/O Output Two-Wire Interface I/O ...
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... Note: No PLLRCA line present on the AT91SAM9G20. 4. Package and Pinout • The AT91SAM9G20 is available in a 217-ball mm, LFBGA package (0.8 mm pitch) (Figure • The AT91SAM9G20 is available in a 247-ball 1.1 mm, TFBGA Green package, (0.5 mm pitch) 4.1 217-ball LFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9G20 Mechanical Charac- teristics” ...
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... NTRST P8 H17 PB18 P9 J1 PC19 P10 J2 PC17 P11 J3 VDDIOM P12 J4 PC16 P13 J8 GND P14 J9 GND P15 J10 GND P16 AT91SAM9G20 Signal Name Pin Signal Name TDO P17 PB5 PB19 R1 NC TDI R2 GNDANA PB16 R3 PC29 PC24 R4 VDDANA PC20 R5 PB12 D15 R6 PB23 PC21 ...
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... TFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9G20 Mechanical Charac- teristics” of the product datasheet. Figure 4-2. 6384E–ATARM–05-Feb-10 shows the orientation of the 247-ball TFBGA package. 247-ball TFBGA Package (Top View) Ball ...
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... DDM P7 J18 VDDIOP P8 K2 GNDPLL P9 K3 GND P10 K5 NC P11 K6 GNDPLL P12 K7 VDDANA P13 K8 GND P14 K9 GND P15 AT91SAM9G20 Signal Name Pin Signal Name GND P17 RTCK VDDIOM P18 PB16 GND R2 GND GND R3 PB29 XOUT32 R5 PB26 XIN32 R6 PB27 HDPA R7 PA5 HDMA ...
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... Power Considerations 5.1 Power Supplies The AT91SAM9G20 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and 1 ...
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... All the I/O lines are Schmitt trigger inputs and all the lines managed by the PIO Controllers inte- grate a programmable pull-up resistor of 75 kΩ typical with the exception P31. For details, refer to the section “AT91SAM9G20 Electrical Characteristics”. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. ...
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... On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit 7.2 Bus Matrix • 6-layer Matrix, handling requests from 6 masters • Programmable Arbitration strategy – Fixed-priority Arbitration 6384E–ATARM–05-Feb-10 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9G20 15 ...
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... Allows Handling of Dynamic Exception Vectors 7.2.1 Matrix Masters The Bus Matrix of the AT91SAM9G20 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available. Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... USART4 Transmit Channel – USART3 Transmit Channel – USART2 Transmit Channel – USART1 Transmit Channel – USART0 Transmit Channel – SPI1 Transmit Channel 6384E–ATARM–05-Feb-10 AT91SAM9G20 Masters to Slaves Access Master 0 & 1 ARM926 Slave Instruction & Data Internal SRAM ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins AT91SAM9G20 18 6384E–ATARM–05-Feb-10 ...
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... Memories Figure 8-1. AT91SAM9G20 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI ...
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... REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted. When REMAP = 1, BMS is ignored. Refer to the Bus Matrix Section for more details. AT91SAM9G20 20 Table 8-1, “Internal Memory Mapping,” on page 20 ...
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... When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: The AT91SAM9G20 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. ...
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... Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Datapath • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached AT91SAM9G20 22 Figure 8-1 on page 19. 6384E–ATARM–05-Feb-10 ...
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... Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path • Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path 6384E–ATARM–05-Feb-10 AT91SAM9G20 23 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes. Figure 9-1 on page 25 Figure 8-1 on page 19 peripherals. AT91SAM9G20 24 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 6384E–ATARM–05-Feb-10 ...
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... System Controller Block Diagram Figure 9-1. AT91SAM9G20 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSCSEL SLOW XIN32 CLOCK OSC XOUT32 XIN MAIN OSC XOUT ...
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... Embeds 2 PLLs – The PLL A outputs 400-800 MHz clock – The PLL B outputs 100 MHz clock – Both integrate an input divider to increase output accuracy – PLL A and PLL B embed their own filters AT91SAM9G20 26 reset, user reset or watchdog reset 6384E–ATARM–05-Feb-10 ...
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... Backup Mode, Main Power Supplies off, VDDBU powered by a battery 6384E–ATARM–05-Feb-10 Clock Generator Block Diagram OSCSEL XIN32 XOUT32 XIN XOUT MCK divider can be 1,2,4,6 processor stopped waiting for an interrupt AT91SAM9G20 Clock Generator On Chip RC OSC Slow Clock SLCK Slow Clock Oscillator Main Main Clock ...
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... Four 32-bit backup general-purpose registers 9.10 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Thirty-two individually maskable and vectored interrupt sources AT91SAM9G20 28 AT91SAM9G20 Power Management Controller Block Diagram Divider Master Clock Controller SLCK Divider Prescaler MAINCK ...
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... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 9.12 Chip Identification • Chip ID:0x019905A1 • JTAG ID: 0x05B2403F • ARM926 TAP ID:0x0792603F 6384E–ATARM–05-Feb-10 enabled processor Generator the ARM Processor’s ICE Interface AT91SAM9G20 ® USART 29 ...
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... AT91SAM9G20 30 defines the Peripheral Identifiers of the AT91SAM9G20. A peripheral identifier is AT91SAM9G20 Peripheral Identifiers (Continued) Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC ADC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC - - TC0 TC1 ...
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... IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.3 Peripheral Signal Multiplexing on I/O Lines The AT91SAM9G20 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions ...
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... PA24 TWCK ETX3 PA25 TCLK0 ERX2 PA26 TIOA0 ERX3 PA27 TIOA1 ERXCK PA28 TIOA2 ECRS PA29 SCK1 ECOL PA30 SCK2 RXD4 PA31 SCK0 TXD4 AT91SAM9G20 32 Application Usage Comments Reset State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP ...
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... TIOB5 I/O ISI_D0 I/O ISI_D1 I/O ISI_D2 I/O ISI_D3 I/O ISI_D4 I/O ISI_D5 I/O ISI_D6 I/O ISI_D7 I/O ISI_PCK I/O ISI_VSYNC I/O ISI_HSYNC I/O ISI_MCK I/O AT91SAM9G20 Application Usage Power Supply Function Comments VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP ...
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... D20 PC21 D21 PC22 D22 PC23 D23 PC24 D24 PC25 D25 PC26 D26 PC27 D27 PC28 D28 PC29 D29 PC30 D30 PC31 D31 AT91SAM9G20 34 Peripheral B Comments Reset State SCK3 AD0 I/O PCK0 AD1 I/O PCK1 AD2 I/O SPI1_NPCS3 AD3 I/O SPI1_NPCS2 A23 SPI1_NPCS1 A24 CFCE1 I/O ...
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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection 6384E–ATARM–05-Feb-10 peripherals Sensors and data per chip select AT91SAM9G20 35 ...
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... Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91SAM9G20, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features ...
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... Embedded pad pull-up 10.4.9 Ethernet 10/100 MAC • Compatibility with IEEE Standard 802.3 6384E–ATARM–05-Feb-10 TC Block 0 (TC0, TC1, TC2) and TC Block 1 (TC3, TC4, TC5) have identical user interfaces. See Figure 8-1, “AT91SAM9G20 Memory Mapping,” on page 19 addresses. AT91SAM9G20 for TC Block 0 and TC Block 1 base 37 ...
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... Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals AT91SAM9G20 38 6384E–ATARM–05-Feb-10 ...
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... The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S • a Memory Management Unit (MMU) • separate instruction and data AMBA AHB bus interfaces • separate instruction and data TCM interfaces 6384E–ATARM–05-Feb-10 ™ integer core AT91SAM9G20 ™ family of general-purpose microproces- 39 ...
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... Block Diagram Figure 11-1. ARM926EJ-S Internal Functional Block Diagram CP15 System Configuration Coprocessor Write Data DTCM Interface Data TCM Data Cache AT91SAM9G20 40 External Coprocessors External Coprocessor Interface ARM9EJ-S Processor Core Instruction Read Data Data Instruction Address Address MMU Instruction Data TLB TLB ...
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... ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. 6384E–ATARM–05-Feb-10 AT91SAM9G20 41 ...
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... Table 11-1 Table 11-1. User and System Mode R10 R11 AT91SAM9G20 42 shows all the registers in all modes. ARM9TDMI Modes and Registers Layout Supervisor Mode Abort Mode ...
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... ARM9TDMI Modes and Registers Layout (Continued) Supervisor Mode Abort Mode R12 R12 R13_SVC R13_ABORT R14_SVC R14_ABORT PC PC CPSR CPSR SPSR_ABOR SPSR_SVC T AT91SAM9G20 Undefined Interrupt Fast Interrupt Mode Mode R12 R12 R13_UNDEF R13_IRQ R14_UNDEF R14_IRQ PC PC CPSR CPSR SPSR_UNDE SPSR_IRQ ...
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... The leged mode. The types of exceptions are: • Fast interrupt (FIQ) • Normal interrupt (IRQ) • Data and Prefetched aborts (Abort) • Undefined instruction (Undefined) • Software interrupt and Reset (Supervisor) AT91SAM9G20 Reserved Jazelle state bit ...
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... Execute stage in the 6384E–ATARM–05-Feb-10 into LR (current PC(r15 depending on the exception). (current depending on the exception) that causes the program to resume from the correct place on return. AT91SAM9G20 45 ...
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... SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB AT91SAM9G20 46 gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply ...
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... Signed Multiply bit Signed Multiply bit Saturated Add Saturated Add with Double Saturated subtract Saturated Subtract with double 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. AT91SAM9G20 Mnemonic Operation STRH Store Half Word STRB Store Byte ...
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... AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC AT91SAM9G20 48 gives the Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply ...
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... Test configuration 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. AT91SAM9G20 Table 11-5. Read/Write Read/Unpredictable ...
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... Determines the destination coprocessor register. • L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM. AT91SAM9G20 50 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 ...
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... When the TLB contains an entry for the MVA (Modi- 6384E–ATARM–05-Feb-10 Mapping Details Mapping Size Access Permission By 1M byte Section 64K bytes 4 separated subpages 4K bytes 4 separated subpages 1K byte Tiny Page AT91SAM9G20 ® , Windows CE, and Subpage Size - 16K bytes 1K byte - 51 ...
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... The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual. AT91SAM9G20 52 6384E–ATARM–05-Feb-10 ...
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... Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the 6384E–ATARM–05-Feb-10 AT91SAM9G20 53 ...
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... When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. AT91SAM9G20 54 6384E–ATARM–05-Feb-10 ...
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... NCB, WT that has missed in DCache) • data read (NCNB or NCB) • NC instruction fetch (prefetched and non-prefetched) • page table walk read Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT write. Full-line cache write-back, eight-word burst NCNB, NCB, WT write. Cache linefill AT91SAM9G20 55 ...
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... AT91SAM9G20 56 6384E–ATARM–05-Feb-10 ...
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... AT91SAM9G20 Debug and Test 12.1 Overview The AT91SAM9G20 features a number of complementary debug and test capabilities. A com- mon JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel ...
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... Block Diagram Figure 12-1. Debug and Test Block Diagram TAP: Test Access Port AT91SAM9G20 58 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ARM926EJ-S PDC DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test DTXD DRXD 6384E–ATARM–05-Feb-10 ...
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... A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. Application Debug and Trace Environment Example 6384E–ATARM–05-Feb-10 shows a complete debug environment example. The ICE/JTAG inter- ICE/JTA ICE/JTAG RS232 AT91SAM9G20 Connector AT91SAM9G20-based Application AT91SAM9G20 Host Debugger Terminal 59 ...
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... Test vectors are sent and inter- Test Adaptor JTAG Interface ICE/JTAG Chip n Connector AT91SAM9G20 AT91SAM9G20-based Application Board In Test Debug and Test Pin List Function Reset/Test Microcontroller Reset Test Mode Select ICE and JTAG Test Reset Signal Test Clock ...
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... TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 6384E–ATARM–05-Feb-10 AT91SAM9G20 ™ is supported via the ICE/JTAG port connected to a ™ ...
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... The Boundary-scan Register (BSR) contains 308 bits that correspond to active pins and associ- ated control signals. Each AT91SAM9G20 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad ...
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... Table 12-2. 6384E–ATARM–05-Feb-10 AT91SAM9G20 JTAG Boundary Scan Register 297 A13 296 295 A14 294 293 A15 292 291 A16 290 289 A17 288 287 A18 286 285 A19 284 283 A2 282 281 A20 280 279 A21 278 277 A22 ...
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... AT91SAM9G20 64 AT91SAM9G20 JTAG Boundary Scan Register CAS D0 D1 D10 D11 D12 D13 D14 D15 NANDOE CONTROL IN/OUT INPUT/OUTPUT ...
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... Table 12-2. 6384E–ATARM–05-Feb-10 AT91SAM9G20 JTAG Boundary Scan Register 224 NANDWE 223 222 NCS0 221 220 NCS1 219 218 NRD 217 216 NRST 215 214 NWR0 213 212 NWR1 211 210 NWR3 209 208 OSCSEL 207 PA0 206 205 PA1 ...
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... AT91SAM9G20 66 AT91SAM9G20 JTAG Boundary Scan Register PA18 PA19 PA2 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA3 PA4 PA5 CONTROL IN/OUT ...
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... Table 12-2. 6384E–ATARM–05-Feb-10 AT91SAM9G20 JTAG Boundary Scan Register 151 PA6 150 149 PA7 148 147 PA8 146 145 PA9 144 143 PB0 142 141 PB1 140 139 PB10 138 137 PB11 136 135 134 133 132 131 PB14 130 ...
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... Table 12-2. 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 AT91SAM9G20 68 AT91SAM9G20 JTAG Boundary Scan Register PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 99 PB29 98 97 PB3 96 95 PB30 94 93 PB31 92 91 PB4 90 89 ...
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... Table 12-2. 6384E–ATARM–05-Feb-10 AT91SAM9G20 JTAG Boundary Scan Register 79 PC0 78 77 PC1 76 75 PC10 74 73 PC11 PC13 68 67 PC14 66 65 PC15 64 63 PC16 62 61 PC17 60 59 PC18 58 57 PC19 PC20 52 51 PC21 50 49 PC22 48 47 PC23 ...
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... Table 12-2. AT91SAM9G20 70 AT91SAM9G20 JTAG Boundary Scan Register 43 PC25 42 41 PC26 40 39 PC27 38 37 PC28 36 35 PC29 PC30 30 29 PC31 28 27 PC4 26 25 PC5 24 23 PC6 22 21 PC7 20 19 PC8 18 17 PC9 16 15 RAS 14 13 RTCK 12 11 SDA10 10 09 SDCK ...
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... Table 12-2. 6384E–ATARM–05-Feb-10 AT91SAM9G20 JTAG Boundary Scan Register 07 SDCKE 06 05 SDWE 04 03 SHDN 02 01 TST 00 WKUP AT91SAM9G20 CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL OUT OUTPUT INPUT INPUT INPUT INPUT 71 ...
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... VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B24 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_403F. AT91SAM9G20 PART NUMBER 13 12 ...
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... AT91SAM9G20 Boot Program 13.1 Overview The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. The Boot program tries to detect SPI flash memories. The Serial Flash Boot program and Data- ® ...
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... Figure 13-1. Boot Program Algorithm Flow Diagram SPI Serialflash Boot No SPI Dataflash Boot No SPI Serialflash Boot No SPI Dataflash Boot No NandFlash Boot No SD Card Boot No EEPROMBoot No AT91SAM9G20 74 Device Setup Yes Download from Serial flash NPCS0 NPCS0 Timeout < Yes Download from NPCS0 Dataflash NPCS0 Timeout < Yes ...
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... Table 13-3 Boot Program. Crystals Supported by Software Auto-Detection (MHz) 3.2768 3.6864 4.608 4.9152 6.144 6.4 7.864320 8.0 12.0 12.288 16.0 17.734470 Booting either on USB or on DBGU is possible with any of these input frequencies. AT91SAM9G20 TTable 18.432 Other Yes Yes Yes Other Yes Yes Yes Yes Yes ...
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... Table 13-4 defines the crystals supported by the Boot Program. Input Frequencies Supported (OSCEL = 1) 3.2768 3.6864 4.608 4.9152 6.144 6.4 7.864320 8.0 12.0 12.288 16.0 17.734470 24.576 25.0 40.0 48.0 Booting either on USB or on DBGU is possible with any of these input frequencies. AT91SAM9G20 3.84 4.0 5.0 5.24288 6.5536 7.159090 9.8304 10.0 13.56 14.31818 18.432 20.0 28.224 32 ...
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... Internal ROM 0x0020_0000 Internal SRAM AT91SAM9G20 0x0000_0000 Internal SRAM REMAP 0x0010_0000 Internal ROM “Structure of ARM Vector 6” on page Offset (24 bits) 77 ...
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... This application may be the application code or a second-level bootloader. 6384E–ATARM–05-Feb-10 Size of the code to download in bytes ea000006 B 0x20 eafffffe B 0x04 ea00002f B _main eafffffe B 0x0c eafffffe B 0x10 <- Code size = 4660 bytes 00001234 B 0x14 eafffffe B 0x18 AT91SAM9G20 0 78 ...
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... LDR or Branch instruction Yes Read the SerialFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91SAM9G20 No Jump to next boot solution No 79 ...
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... LDR or Branch instruction Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91SAM9G20 No Jump to next boot solution No 80 ...
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... TWI address: 0x0050_0000 valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See more information on Valid Image Detection. 6384E–ATARM–05-Feb-10 AT91SAM9G20 “Valid Image Detection” on page 77 “Valid Image Detection” on page 77 for for ...
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... Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the SAM-BA boot version – Output: ‘>’ AT91SAM9G20 82 loop waiting for different commands as in Commands Available through the SAM-BA Boot Action ...
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... CRC16 Figure 13-8 Figure 13-8. Xmodem Transfer Example 6384E–ATARM–05-Feb-10 to 01) shows a transmission using this protocol. Host SOH 01 FE Data[128] CRC CRC SOH 02 FD Data[128] CRC CRC SOH 03 FC Data[100] CRC CRC AT91SAM9G20 Device C ACK ACK ACK EOT ACK 83 ...
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... The device also handles some class requests defined in the CDC class. Table 13-7. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Unhandled requests are STALLed. AT91SAM9G20 84 ® , from Windows 98SE to Windows XP Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. ...
Page 85
... Endpoint 64-byte Bulk OUT endpoint and endpoint 64-byte Bulk IN endpoint. SAM- BA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 6384E–ATARM–05-Feb-10 AT91SAM9G20 85 ...
Page 86
... MCI0 MCI0 MCI0 MCI0 TWI TWI DBGU DBGU AT91SAM9G20 86 1. Boot ROM does not support high capacity SDCards. contains a list of pins that are driven during the boot program execution. These pins Pins Driven during Boot Program Execution Pin MOSI MISO SPCK ...
Page 87
... Block Diagram Figure 14-1. Reset Controller Block Diagram Backup Supply 6384E–ATARM–05-Feb-10 Reset Controller Main Supply POR Startup POR Counter NRST NRST Manager nrst_out WDRPROC wd_fault AT91SAM9G20 rstc_irq Reset State Manager proc_nreset user_reset periph_nreset exter_nreset backup_neset SLCK 87 ...
Page 88
... The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN RSTC_MR disables the User Reset trigger. AT91SAM9G20 88 Figure 14-2 shows the block diagram of the NRST Manager. ...
Page 89
... Startup Counter, which operates at Slow Clock. The pur- pose of this counter is to make sure the Slow Clock oscillator is stable before starting up the 6384E–ATARM–05-Feb-10 Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs XXX BMS sampling delay = 3 cycles AT91SAM9G20 ...
Page 90
... SLCK MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) AT91SAM9G20 90 shows how the General Reset affects the reset signals. Startup Time Processor Startup = 3 cycles XXX EXTERNAL RESET LENGTH = 2 cycles Any Freq. 0x0 = General Reset ...
Page 91
... The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. 6384E–ATARM–05-Feb-10 Resynch. Processor Startup 2 cycles = 3 cycles XXX EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) AT91SAM9G20 Any Freq. 0x1 = WakeUp Reset XXX 91 ...
Page 92
... Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn- chronously to SLCK. AT91SAM9G20 Resynch ...
Page 93
... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. 6384E–ATARM–05-Feb-10 Any Freq. Resynch. Processor Startup 1 cycle = 3 cycles XXX Any EXTERNAL RESET LENGTH AT91SAM9G20 0x3 = Software Reset 8 cycles (ERSTL=2) 93 ...
Page 94
... When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. AT91SAM9G20 94 Any Freq. Processor Startup = 3 cycles ...
Page 95
... URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 6384E–ATARM–05-Feb-10 AT91SAM9G20 read RSTC_SR 2 cycle resynchronization Figure 95 ...
Page 96
... Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. AT91SAM9G20 96 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Back-up Reset ...
Page 97
... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6384E–ATARM–05-Feb- KEY – – – – – – – – EXTRST AT91SAM9G20 – – – PERRST – PROCRST 24 16 – 8 – ...
Page 98
... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. AT91SAM9G20 – ...
Page 99
... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6384E–ATARM–05-Feb- KEY – – – – – URSTIEN – AT91SAM9G20 – – ERSTL – – URSTEN (ERSTL+1) Slow Clock cycles. This 99 ...
Page 100
... AT91SAM9G20 100 6384E–ATARM–05-Feb-10 ...
Page 101
... RTT_SR RTTINC reset 1 0 32-bit Counter read RTT_SR reset CRTV RTT_SR ALMS set = ALMV AT91SAM9G20 RTT_MR RTTINCIEN rtt_int RTT_MR ALMIEN rtt_alarm 32 seconds, corre- 101 ...
Page 102
... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM9G20 102 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
Page 103
... Real-time Timer (RTT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6384E–ATARM–05-Feb-10 AT91SAM9G20 Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 ...
Page 104
... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM9G20 104 – ...
Page 105
... Returns the current value of the Real-time Timer. 6384E–ATARM–05-Feb- ALMV ALMV ALMV ALMV CRTV CRTV CRTV CRTV AT91SAM9G20 105 ...
Page 106
... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM9G20 106 – ...
Page 107
... Periodic Interval Counter, PICNT. The status bit PITS in the Status Regis- ter (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). 6384E–ATARM–05-Feb-10 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR AT91SAM9G20 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR ...
Page 108
... PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface AT91SAM9G20 108 APB cycle MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR Figure 16-2 APB cycle ...
Page 109
... Periodic Interval Timer (PIT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register 6384E–ATARM–05-Feb-10 AT91SAM9G20 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset 0x000F_FFFF 0x0000_0000 ...
Page 110
... PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. AT91SAM9G20 110 – ...
Page 111
... PICNT CPIV CPIV AT91SAM9G20 – – – – – – – – – – – PITS CPIV ...
Page 112
... Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 6384E–ATARM–05-Feb- PICNT CPIV CPIV AT91SAM9G20 CPIV 112 ...
Page 113
... WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6384E–ATARM–05-Feb-10 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset AT91SAM9G20 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 113 ...
Page 114
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM9G20 114 6384E–ATARM–05-Feb-10 ...
Page 115
... Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6384E–ATARM–05-Feb-10 Watchdog Error WDT_CR = WDRSTT AT91SAM9G20 Watchdog Underflow if WDRSTEN WDRSTEN is 0 115 ...
Page 116
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9G20 116 Name WDT_CR WDT_MR WDT_SR KEY – ...
Page 117
... The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 6384E–ATARM–05-Feb- WDDBGHLT WDD WDFIEN WDV AT91SAM9G20 WDD WDV 117 ...
Page 118
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM9G20 118 – ...
Page 119
... The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Con- troller has no effect on the behavior of the Shutdown Controller. 6384E–ATARM–05-Feb-10 read SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset RTTWK SHDW_MR SHDW_SR set AT91SAM9G20 SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW Type Input Output 119 ...
Page 120
... SHDW_SR. When using the RTT alarm to wake up the system, the user must ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails. AT91SAM9G20 120 6384E–ATARM–05-Feb-10 ...
Page 121
... Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6384E–ATARM–05-Feb-10 AT91SAM9G20 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0003 0x0000_0000 121 ...
Page 122
... SHDW: Shutdown Command effect KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9G20 122 KEY – – ...
Page 123
... Wake-up Input Transition Selection None. No detection is performed on the wake-up input Low to high level High to low level Both levels change AT91SAM9G20 26 25 – – – – – – – – – ...
Page 124
... At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. • RTTWK: Real-time Timer Wake- wake-up alarm from the RTT occurred since the last read of SHDW_SR least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. AT91SAM9G20 124 – ...
Page 125
... AT91SAM9G20 Bus Matrix 19.1 Overview The Bus Matrix implements a multi-layer AHB based on the AHB-Lite protocol that enables par- allel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects 6 AHB Masters to 5 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency) ...
Page 126
... INCR transfer. 4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). AT91SAM9G20 126 126. Section 19.4.1.1 “Undefined Length 126). 127). ...
Page 127
... For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and MATRIX_PRBS). 6384E–ATARM–05-Feb-10 AT91SAM9G20 127 ...
Page 128
... Priority Register A for Slave 2 0x0094 Reserved 0x0098 Priority Register A for Slave 3 0x009C Reserved 0x00A0 Priority Register A for Slave 4 0x00A8 - 0x00FC Reserved 0x0100 Master Remap Control Register 0x0104 - 0x010C Reserved AT91SAM9G20 128 Name Access MATRIX_MCFG0 Read-write MATRIX_MCFG1 Read-write MATRIX_MCFG2 Read-write MATRIX_MCFG3 Read-write MATRIX_MCFG4 Read-write MATRIX_MCFG5 Write-only – ...
Page 129
... The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 6384E–ATARM–05-Feb- – – – – – – – – – – – – AT91SAM9G20 – – – – – – – – – ULBT 129 ...
Page 130
... This is the number of the Default Master for this slave. Only used if DEFMASTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMASTR_TYPE to 0. • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration 2: Reserved 3: Reserved AT91SAM9G20 130 – – ...
Page 131
... Fixed priority of Master x for access to the selected slave. The higher the number, the higher the priority. 6384E–ATARM–05-Feb- – – – M5PR – M3PR – M1PR – AT91SAM9G20 – – – – M4PR – M2PR – M0PR 131 ...
Page 132
... RCBx: Remap Command Bit for AHB Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master AT91SAM9G20 132 – – – – – ...
Page 133
... EBI D0 - D15 Data Bus bits are not internally pulled-up. 6384E–ATARM–05-Feb- – – – – – – EBI_CS5A EBI_CS4A EBI_CS3A AT91SAM9G20 Name Access – – EBI_CSA Read-write – – – – – – ...
Page 134
... VDDIOMSEL: Memory voltage selection 0 = Memories are 1.8V powered Memories are 3.3V powered. • IOSR: I/O Slew Rate Selection Refer to the” I/Os” sub-section of the “Clock Characteristics” in the product “Electrical Characteristics”. AT91SAM9G20 134 6384E–ATARM–05-Feb-10 ...
Page 135
... AT91SAM9G20 External Bus Interface 20.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI ...
Page 136
... Block Diagram 20.2.1 External Bus Interface Figure 20-1 Figure 20-1. Organization of the External Bus Interface Bus Matrix AHB Address Decoders AT91SAM9G20 136 shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Static Logic Memory Controller CompactFlash Logic NAND Flash Logic ...
Page 137
... EBI_NWR0 - EBI_NWR3 Write Signals EBI_NBS0 - EBI_NBS3 Byte Mask Signals EBI_SDA10 SDRAM Address 10 Line 6384E–ATARM–05-Feb-10 EBI SMC EBI for CompactFlash Support EBI for NAND Flash Support SDRAM Controller AT91SAM9G20 Type Active Level I/O Output Input Low Output Low Output Low Output ...
Page 138
... The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 20-2 on page 138 EBI pins. Table 20-2. AT91SAM9G20 138 details the connections between the two Memory Controllers and the EBI Pins and Memory Controllers I/O Lines Connections EBIx Pins ...
Page 139
... A[1:21] A[1:21] A[22:24] A[22:24 ( (1) WE NUB – – AT91SAM9G20 4 x 8-bit 2 x 16-bit 32-bit Static Static Static Devices Devices D15 D16 - D23 D24 - D31 (3) – NLB (2) (4) WE NLB A[0:20] A[0:20] A[21:23] A[21:23 ...
Page 140
... A21/NANDALE A22/NANDCLE A23 - A24 A25 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 NCS6 NCS7 NANDOE NANDWE NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW CFCE1 AT91SAM9G20 140 Pins of the Interfaced Device CompactFlash SDRAM (EBI only) SDRAMC D15 D16 - D31 – DQM0 A0 DQM2 A1 A[0:8] A[2:10] A9 – ...
Page 141
... CLK – CKE – RAS – CAS – WE – – WAIT – CD1 or CD2 – – – – AT91SAM9G20 CompactFlash True IDE Mode NAND Flash (EBI only) SMC CS1 – – – – – – – – – – – WAIT – ...
Page 142
... It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: • the Static Memory Controller (SMC) • the SDRAM Controller (SDRAMC) AT91SAM9G20 142 shows an example of connections between the EBI and external devices. EBI ...
Page 143
... FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup- ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. 6384E–ATARM–05-Feb-10 AT91SAM9G20 143 ...
Page 144
... Register (DBW field in the corresponding Chip Select Register) of the NCS4 and/or NCS5 address space must be set as shown in NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select. AT91SAM9G20 144 144. Offset 0x00E0 0000 ...
Page 145
... Access to Odd Byte on D[15:8] Don’t 1 Access to Even Byte on D[7:0] Care 1 8 bits Access to Odd Byte on D[7:0] 1 – demonstrates a schematic representation of this logic. AT91SAM9G20 SMC Access Mode Byte Select Byte Select Byte Select Byte Select Don’t Care – – Figure 145 ...
Page 146
... EBI_CSA Register in the Chip Configuration User Interface is set. These pins must not be used to drive any other memory devices. The EBI pins in responding CompactFlash interface is enabled (EBI_CS4A = 1 and/or EBI_CS5A = 1). Table 20-8. Dedicated CompactFlash Interface Multiplexing Pins CS4A = 1 NCS4/CFCS0 CFCS0 NCS5/CFCS1 AT91SAM9G20 146 External Bus Interface SMC A23 A22 NRD_NOE NWR0_NWE CFWE NRD NWR0_NWE ...
Page 147
... Memory Controller (SMC)”. 6384E–ATARM–05-Feb-10 Access to CompactFlash Device CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW illustrates an example of a CompactFlash application. CFCS0 and AT91SAM9G20 Access to Other EBI Devices EBI Signals NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 A25 147 ...
Page 148
... Programming the EBI_CS3A field in the EBI_CSA Register in the Chip Configuration User Inter- face to the appropriate value enables the NAND Flash logic. For details on this register, refer to the section “AT91SAM9G20 Bus Matrix”. Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF) ...
Page 149
... Note: 6384E–ATARM–05-Feb-10 SMC NCSx NRD_NOE NWR0_NWE D[7:0] A[22:21] NCSx/NANDCS EBI NANDOE NANDWE PIO PIO The External Bus Interface is also able to support 16-bit devices. AT91SAM9G20 NAND Flash Logic NANDOE NANDWE AD[7:0] ALE CLE Not Connected NAND Flash NOE NWE CE R/B NANDOE NANDWE 149 ...
Page 150
... Select Assignment Register located in the bus matrix memory space. • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width programmed to 16 bits. The SDRAM initialization sequence is described in the “SDRAM device initialization” part of the SDRAM controller. AT91SAM9G20 150 D[0..15] A[0..14] (Not used A12) ...
Page 151
... C7 100NF C7 100NF DQML VDDQ 39 DQMH 28 VSS 17 41 CAS VSS 18 54 RAS VSS 6 VSSQ 12 VSSQ VSSQ VSSQ 256 Mbits TSOP54 PACKAGE AT91SAM9G20 DQ0 MT48LC16M16A2 MT48LC16M16A2 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 ...
Page 152
... A21 and A22 during accesses. • Configure a PIO line as an input to manage the Ready/Busy signal. • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. AT91SAM9G20 152 U1 U1 ...
Page 153
... R/B 10K 10K 3V3 10K 10K 1 N.C 2 N.C 3 N.C 4 N.C 5 N.C 6 N.C 10 N.C 11 N.C 14 N.C 15 N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 N.C 34 N.C 35 N.C AT91SAM9G20 MT29F2G16AABWP-ET MT29F2G16AABWP I/O9 D10 31 I/O10 D11 33 I/O11 D12 41 I/O12 D13 43 I/O13 D14 45 I/O14 D15 47 ...
Page 154
... The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. AT91SAM9G20 154 D[0..15] A[1..22] ...
Page 155
... RDY/BSY 11 12 3V3 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K WAIT GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 AT91SAM9G20 MEMORY & I/O MODE J1 J1 CF_D15 31 38 D15 VCC CF_D14 30 D14 CF_D13 29 13 D13 VCC CF_D12 28 D12 CF_D11 27 D11 CF_D10 49 50 ...
Page 156
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9G20 156 6384E–ATARM–05-Feb-10 ...
Page 157
... INTRQ 11 12 3V3 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K IORDY GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 AT91SAM9G20 TRUE IDE MODE J1 J1 CF_D15 31 38 D15 VCC CF_D14 30 D14 CF_D13 29 13 D13 VCC CF_D12 28 D12 CF_D11 27 D11 CF_D10 49 50 ...
Page 158
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9G20 158 6384E–ATARM–05-Feb-10 ...
Page 159
... Write or Byte Select Access” on page 161 8-/16-bit or 32-bit data bus, see “Data Bus Width” on page Byte-write or byte-select access, see Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 161 AT91SAM9G20 Type Output Output Output Output Output ...
Page 160
... The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. AT91SAM9G20 160 128K x 8 SRAM ...
Page 161
... This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 6384E–ATARM–05-Feb-10 NCS2 NCS1 NCS0 shows how to connect a 512K x 8-bit memory on NCS2. Figure 21-5 AT91SAM9G20 Figure 21-2). NCS7 Memory Enable NCS6 Memory Enable NCS5 Memory Enable ...
Page 162
... Figure 21-3. Figure 21-4. Figure 21-5. Memory Connection for a 32-bit Data Bus AT91SAM9G20 162 Memory Connection for an 8-bit Data Bus D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] Memory Connection for a 16-bit Data Bus D[15:0] A[19:2] A1 NBS0 SMC NBS1 NWE NRD NCS[2] D[31:16] D[15:0] A[20:2] NBS0 SMC NBS1 NBS2 NBS3 NWE NRD NCS[2] ...
Page 163
... Byte Select Access is used to connect two 16-bit devices. Figure 21-7 mode, on NCS3 (BAT = Byte Select Access). 6384E–ATARM–05-Feb-10 Figure 21-6. shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access AT91SAM9G20 163 ...
Page 164
... For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. AT91SAM9G20 164 Connection 8-bit Devices on a 16-bit Bus: Byte Write Option ...
Page 165
... Byte Select Byte Write Byte Select NBS0 NWE NWR0 NBS1 NWR1 NBS2 NWR2 NBS3 NWR3 AT91SAM9G20 D[15:0] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable ...
Page 166
... NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. AT91SAM9G20 166 Figure 21-8. MCK A[25:2] ...
Page 167
... NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 21.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see 6384E–ATARM–05-Feb-10 AT91SAM9G20 Figure 21-9). 167 ...
Page 168
... NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. AT91SAM9G20 168 MCK A[25:2] ...
Page 169
... Figure 21-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS NBS0,NBS1, NBS2,NBS3, A0, A1 6384E–ATARM–05-Feb-10 MCK A[25:2] NRD NCS D[31:0] shows the typical read cycle of an LCD module. The read data is valid t MCK A[25:2] NRD NCS D[31:0] AT91SAM9G20 t PACC Data Sampling t PACC Data Sampling after PACC 169 ...
Page 170
... NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 21-12. Write Cycle NBS0, NBS1, NBS2, NBS3, A0, A1 AT91SAM9G20 170 MCK [25:2] A NWE NCS NWE_SETUP ...
Page 171
... Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. 6384E–ATARM–05-Feb-10 MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NCS D[31:0] NWE_PULSE NCS_WR_PULSE NWE_CYCLE AT91SAM9G20 Figure NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE 21-13). How- 171 ...
Page 172
... NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. AT91SAM9G20 172 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is ...
Page 173
... NCS D[31:0] shows how the timing parameters are coded and their permitted range. Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] AT91SAM9G20 Permitted Range Coded Value Effective Value 0 ≤ ≤ 31 128 ≤ ≤ 128+31 0 ≤ ≤ 63 256 ≤ ≤ 256+63 256 ≤ ...
Page 174
... During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD lines are all set to 1. Figure 21-16 Select 2. AT91SAM9G20 174 gives the default value of timing parameters at reset. “Early Read Wait State” on page 175. ...
Page 175
... Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 21-17. 6384E–ATARM–05-Feb-10 NCS2 MCK NRD NWE NRD_CYCLE (Figure 21-18). Figure AT91SAM9G20 NWE_CYCLE Read to Write Chip Select Wait State Wait State 21-20. (Figure 175 ...
Page 176
... D[31:0] Figure 21-19. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD D[31:0] AT91SAM9G20 176 no hold write cycle Early Read wait state no hold write cycle Early Read (READ_MODE = 0 or READ_MODE = 1) (WRITE_MODE = 0) ...
Page 177
... A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see 6384E–ATARM–05-Feb-10 MCK no hold NRD write cycle Early Read (WRITE_MODE = 1) wait state AT91SAM9G20 read setup = 1 read cycle (READ_MODE = 0 or READ_MODE = 1) “Slow Clock Mode” on page 189). 177 ...
Page 178
... SMC accesses. This wait cycle is referred read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See AT91SAM9G20 178 Figure 21-16 on page 175. 6384E–ATARM–05-Feb-10 ...
Page 179
... NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. 6384E–ATARM–05-Feb-10 ) for each external memory device is programmed in the DF will not slow down the execution of a program from internal DF illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), AT91SAM9G20 Figure 21-22 shows the read oper- 179 ...
Page 180
... Figure 21-21. TDF Period in NRD Controlled Read Access (TDF = 2) Figure 21-22. TDF Period in NCS Controlled Read Operation (TDF = 3) AT91SAM9G20 180 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NRD NCS tpacc D[31:0] NRD controlled read operation MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS tpacc D[31:0] NCS controlled read operation ...
Page 181
... TDF optimization. 6384E–ATARM–05-Feb-10 shows a read access controlled by NRD, followed by a write access controlled by NRD_HOLD= 4 TDF_CYCLES = 6 Read to Write Wait State 21-24, Figure 21-25 and Figure 21-26 AT91SAM9G20 NWE_SETUP= 3 write access on NCS0 (NWE controlled) illustrate the cases: 181 ...
Page 182
... A NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 cycle TDF_CYCLES = 4 AT91SAM9G20 182 read1 hold = 1 TDF_CYCLES = 6 5 TDF WAIT STATES Chip Select Wait State read1 hold = 1 TDF_CYCLES = 4 2 TDF WAIT STATES Read to Write Chip Select Wait State ...
Page 183
... The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. 6384E–ATARM–05-Feb-10 read1 hold = 1 TDF_CYCLES = 5 read1 cycle Read to Write Wait State AT91SAM9G20 write2 setup = 1 4 TDF WAIT STATES write2 cycle TDF_MODE = 0 (optimization disabled) 192 Slow Clock Mode (“Slow Clock Mode” on ...
Page 184
... The assertion of the NWAIT signal outside the expected period is ignored as illustrated in 21-28. Figure 21-27. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal AT91SAM9G20 184 FROZEN STATE Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 1 ...
Page 185
... A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal 6384E–ATARM–05-Feb-10 FROZEN STATE Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 AT91SAM9G20 Assertion is ignored 0 0 185 ...
Page 186
... Figure 21-29. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal AT91SAM9G20 186 Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 Figure 21-29 and Figure 21-30. After ...
Page 187
... Figure 21-30. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal 6384E–ATARM–05-Feb- Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 AT91SAM9G20 Wait STATE Assertion is ignored 187 ...
Page 188
... NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 21-31. NWAIT Latency MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWAIT intenally synchronized NWAIT signal AT91SAM9G20 188 minimal pulse length NWAIT latency 2 cycle resynchronization Read cycle EXNW_MODE = READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 ...
Page 189
... They are valid on all Table 21-5 indicates the value of read and write parameters in slow clock mode Read and Write Timing Parameters in Slow Clock Mode Duration (cycles AT91SAM9G20 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD 1 1 NCS NRD_CYCLE = 2 SLOW CLOCK MODE READ ...
Page 190
... NBS0, NBS1, NBS2, NBS3, A0,A1 NWE NCS SLOW CLOCK MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition AT91SAM9G20 190 illustrates the recommended procedure to properly switch from one mode to the NWE_CYCLE = 3 ...
Page 191
... Figure 21-34. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK MODE WRITE 6384E–ATARM–05-Feb- IDLE STATE AT91SAM9G20 NORMAL MODE WRITE Reload Configuration Wait State 191 ...
Page 192
... NCS D[31:0] The NRD and NCS signals are held low during all read transfers, whatever the programmed val- ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS AT91SAM9G20 192 ) as shown in sa Page Address and Data Address within a Page ...
Page 193
... Access time of subsequent accesses in the page sa ‘x’ No impact ) and the NRD_PULSE for accesses to the page ( shorter than the programmed value for Figure 21- AT91SAM9G20 Table 21- Table 21-6 are identical, then the cur- illustrates access to an 8-bit memory device in ), even if sa 193 ...
Page 194
... Figure 21-36. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] AT91SAM9G20 194 Page address A1 D1 NRD_PULSE NCS_RD_PULSE NRD_PULSE 6384E–ATARM–05-Feb-10 ...
Page 195
... SMC Mode Register 6384E–ATARM–05-Feb-10 Table 21-8. For each chip select, a set of 4 registers is used to pro- Table 21-8, “CS_number” denotes the chip select number. Name Access SMC_SETUP Read-write SMC_PULSE Read-write SMC_CYCLE Read-write SMC_MODE Read-write AT91SAM9G20 Reset 0x00000000 0x01010101 0x00030003 0x10001000 195 ...
Page 196
... The NRD signal setup length is defined in clock cycles as: NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles • NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles AT91SAM9G20 196 ...
Page 197
... The NCS pulse length must be at least 1 clock cycle. In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page. 6384E–ATARM–05-Feb- NCS_RD_PULSE NRD_PULSE NCS_WR_PULSE NWE_PULSE AT91SAM9G20 197 ...
Page 198
... The total read cycle length is the total duration in clock cycles of the read cycle equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles AT91SAM9G20 198 – ...
Page 199
... NWAIT returns high. 6384E–ATARM–05-Feb- – – TDF_MODE DBW – EXNW_MODE – NWAIT Mode 0 Disabled 1 Reserved 0 Frozen Mode 1 Ready Mode AT91SAM9G20 – – PMEN TDF_CYCLES – – BAT – WRITE_MODE READ_MODE 199 ...
Page 200
... PMEN: Page Mode Enabled 1: Asynchronous burst read in page mode is applied on the corresponding chip select. 0: Standard read is applied. • PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes AT91SAM9G20 200 Data Bus Width 0 8-bit bus 1 16-bit bus 0 32-bit bus 1 ...