ATtiny85 Atmel Corporation, ATtiny85 Datasheet - Page 51

• Manufacturer Part Number: ATtiny85
• Manufacturer: Atmel Corporation

Specifications of ATtiny85

• Flash (kbytes): 8 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.2
9.2.1
2586N–AVR–04/11
External Interrupts
Low Level Interrupt
A typical and general setup for interrupt vector addresses in ATtiny25/45/85 is shown in the pro-
gram example below.
Note:
The External Interrupts are triggered by the INT0 pin or any of the PCINT[5:0] pins. Observe
that, if enabled, the interrupts will trigger even if the INT0 or PCINT[5:0] pins are configured as
outputs. This feature provides a way of generating a software interrupt. Pin change interrupts
PCI will trigger if any enabled PCINT[5:0] pin toggles. The PCMSK Register control which pins
contribute to the pin change interrupts. Pin change interrupts on PCINT[5:0] are detected asyn-
chronously. This implies that these interrupts can be used for waking the part also from sleep
modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt is
enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held
low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an
I/O clock, described in
A low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be
used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in
all sleep modes except Idle mode.
Assembly Code Example
.org 0x0000
RESET:
rjmp RESET
rjmp INT0_ISR
rjmp PCINT0_ISR
rjmp TIM1_COMPA_ISR
rjmp TIM1_OVF_ISR
rjmp TIM0_OVF_ISR
rjmp EE_RDY_ISR
rjmp ANA_COMP_ISR
rjmp ADC_ISR
rjmp TIM1_COMPB_ISR
rjmp TIM0_COMPA_ISR
rjmp TIM0_COMPB_ISR
rjmp WDT_ISR
rjmp USI_START_ISR
rjmp USI_OVF_ISR
<instr>
...
See
“Code Examples” on page
“Clock Systems and their Distribution” on page
6.
;Set address of next statement
; Address 0x0000
; Address 0x0001
; Address 0x0002
; Address 0x0003
; Address 0x0004
; Address 0x0005
; Address 0x0006
; Address 0x0007
; Address 0x0008
; Address 0x0009
; Address 0x000A
; Address 0x000B
; Address 0x000C
; Address 0x000D
; Address 0x000E
; Main program start
; Address 0x000F
ATtiny25/45/85
23.
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