ATtiny85 Atmel Corporation, ATtiny85 Datasheet

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ATtiny85

Manufacturer Part Number
ATtiny85
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny85

Flash (kbytes)
8 Kbytes
Pin Count
8
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
3
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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Features
High Performance, Low Power AVR
Advanced RISC Architecture
Non-volatile Program and Data Memories
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage
Speed Grade
Industrial Temperature Range
Low Power Consumption
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– 2/4/8K Bytes of In-System Programmable Program Memory Flash
– 128/256/512 Bytes In-System Programmable EEPROM
– 128/256/512 Bytes Internal SRAM
– Programming Lock for Self-Programming Flash Program and EEPROM Data
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
– USI – Universal Serial Interface with Start Condition Detector
– 10-bit ADC
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– Six Programmable I/O Lines
– 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V)
– 1.8 - 5.5V for ATtiny25V/45V/85V
– 2.7 - 5.5V for ATtiny25/45/85
– ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
– Active Mode:
– Power-down Mode:
Security
• Endurance: 10,000 Write/Erase Cycles
• Endurance: 100,000 Write/Erase Cycles
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
• 4 Single Ended Channels
• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
• Temperature Measurement
• 1 MHz, 1.8V: 300 µA
• 0.1 µA at 1.8V
®
8-Bit Microcontroller
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny25/V
ATtiny45/V
ATtiny85/V
Summary
Rev. 2586NS–AVR–04/11

Related parts for ATtiny85

ATtiny85 Summary of contents

Page 1

... ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Industrial Temperature Range • Low Power Consumption – Active Mode: • 1 MHz, 1.8V: 300 µA – Power-down Mode: • 0.1 µA at 1.8V ® 8-Bit Microcontroller 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny25/V ATtiny45/V ATtiny85/V Summary Rev. 2586NS–AVR–04/11 ...

Page 2

Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect 1.1 Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND ...

Page 3

The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions ...

Page 4

Overview The ATtiny25/45/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...

Page 5

The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATtiny25/45/85 provides the following features: 2/4/8K ...

Page 6

About 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. ...

Page 7

Register Summary Address Name Bit 7 0x3F SREG I 0x3E SPH – 0x3D SPL SP7 0x3C Reserved 0x3B GIMSK – 0x3A GIFR – 0x39 TIMSK – 0x38 TIFR – 0x37 SPMCSR – 0x36 Reserved 0x35 MCUCR BODS 0x34 MCUSR ...

Page 8

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...

Page 9

Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

Page 10

Mnemonics Operands ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from T to Register SEC Set Carry ...

Page 11

Ordering Information 6.1 ATtiny25 (1) Speed (MHz) Supply Voltage (V) 10 1.8 – 5.5 20 2.7 – 5.5 Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green, and they comply ...

Page 12

ATtiny45 (1) Speed (MHz) Supply Voltage (V) 10 1.8 – 5.5 20 2.7 – 5.5 Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green and they comply with the European ...

Page 13

... Temperature Range Package 8P3 Industrial 8S2 (4) (-40°C to +85°C) 20M1 8P3 Industrial 8S2 (4) (-40°C to +85°C) 20M1 21.3 “Speed” on page 168. Package Types ATtiny25/45/85 (2) (3) Ordering Code ATtiny85V-10PU ATtiny85V-10SU ATtiny85V-10SUR ATtiny85V-10SH ATtiny85V-10MU ATtiny85V-10MUR ATtiny85-20PU ATtiny85-20SU ATtiny85-20SUR ATtiny85-20SH ATtiny85-20MU ATtiny85-20MUR 13 ...

Page 14

Packaging Information 7.1 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...

Page 15

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. ...

Page 16

S8S1 Top View e Side View L End View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny25/45/ ...

Page 17

Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC. 2325 Orchard Parkway San Jose, CA 95131 R 2586NS–AVR–04/ ...

Page 18

D 1 Pin TOP VIEW D2 Pin #1 Notch (0. BOTTOM VIEW Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. Note: 2325 Orchard Parkway San Jose, CA 95131 R ATtiny25/45/85 18 ...

Page 19

Errata 8.1 Errata ATtiny25 The revision letter in this section refers to the revision of the ATtiny25 device. 8.1.1 Rev D and E No known errata. 8.1.2 Rev B and C • EEPROM read may fail at low supply ...

Page 20

Rev B and C • PLL not locking • EEPROM read from application code does not work in Lock Bit Mode 3 • EEPROM read may fail at low supply voltage / low clock frequency • Timer Counter 1 ...

Page 21

The EEPROM is read before entering power down. – VCC is 4.5 volts or higher. Problem fix / Workaround – When using external clock, avoid setting the clock pin as Output. – Do not read the EEPROM if power ...

Page 22

... Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 8.3.1 Rev B and C No known errata. 8.3.2 Rev A • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data ...

Page 23

Datasheet Revision History 9.1 Rev. 2586N-04/11 1. Added: – Section 2. Updated: – Document template. – Removed “Preliminary” on front page. All devices now final and in production. – Section – Program example on – Section – – Section ...

Page 24

Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]. 9.4 Rev. 2586K-01/08 1. Updated Document Template. 2. Added Sections: – – – 3. Updated Sections: – – – – – – – – – – ...

Page 25

... ADTS[2:0]: ADC Auto Trigger Source” on page 142 “SPMCSR – Store Program Memory Control and Status Register” on page “Errata ATtiny25” on page 217 “Errata ATtiny45” on page 217 “Errata ATtiny85” on page 220 “ATtiny25” on page 209 “ATtiny45” on page 210 “ATtiny85” on page 211 “ ...

Page 26

Rev. 2586I-09/ ATtiny25/45/85 26 Updated “Bit 0” in “PRR ...

Page 27

Rev. 2586H-06/ 9.8 Rev. 2586G-05/ 10. 11. 9.9 Rev. 2586F-04/ 9.10 Rev. 2586E-03/ ...

Page 28

Rev. 2586D-02/ 9.12 Rev. 2586C-06/ 9.13 Rev. 2586B-05/ 9.14 Rev. 2586A-02/05 Initial revision. ATtiny25/45/85 28 ...

Page 29

ATtiny25/45/85 29 ...

Page 30

... Atmel Corporation. All rights reserved. ® Atmel , logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Limited Atmel Munich GmbH Unit 01-5 & ...

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