ATtiny85 Atmel Corporation, ATtiny85 Datasheet - Page 106

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ATtiny85

Manufacturer Part Number
ATtiny85
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny85

Flash (kbytes)
8 Kbytes
Pin Count
8
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
3
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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13.3.5
13.3.6
13.3.7
106
ATtiny25/45/85
OCR1C – Timer/Counter1 Output Compare Register C
TIMSK – Timer/Counter Interrupt Mask Register
TIFR – Timer/Counter Interrupt Flag Register
The Output Compare Register B - OCR1B from ATtiny15 is replaced with the output compare
register C - OCR1C that is an 8-bit read/write register. This register has the same function as the
Output Compare Register B in ATtiny15.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C
value. A software write that sets TCNT1 and OCR1C to the same value does not generate a
compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector
$003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one)
in the Timer/Counter Interrupt Flag Register.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is
executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the
Timer/Counter Interrupt Flag Register - TIFR.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
Bit
0x2D
Read/Write
Initial value
Bit
0x39
Read/Write
Initial value
Bit
0x38
Read/Write
Initial value
MSB
R/W
R
R
7
0
7
0
7
1
OCIE1A
OCF1A
R/W
R/W
R/W
6
1
6
0
6
0
OCIE1B
R/W
OCF1B
5
1
R/W
R/W
5
0
5
0
R/W
OCIE0A
4
1
R/W
OCF0A
4
0
R/W
4
0
R/W
3
1
OCIE0B
OCF0B
R/W
R/W
3
0
3
0
R/W
2
1
TOIE1
TOV1
R/W
R/W
2
0
2
0
R/W
1
1
TOIE0
TOV0
R/W
R/W
1
0
1
0
LSB
R/W
0
1
R
0
0
2586N–AVR–04/11
R
0
0
OCR1C
TIMSK
TIFR

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