ATtiny85 Atmel Corporation, ATtiny85 Datasheet - Page 120

• Manufacturer Part Number: ATtiny85
• Manufacturer: Atmel Corporation

Specifications of ATtiny85

• Flash (kbytes): 8 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.5.4
120
ATtiny25/45/85
USICR – USI Control Register
The USI Control Register includes bits for interrupt enable, setting the wire mode, selecting the
clock and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt
and USISIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed
immediately. Refer to the USISIF bit description on
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt and
USIOIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed imme-
diately. Refer to the USIOIF bit description on
• Bits 5:4 – USIWM[1:0]: Wire Mode
These bits set the type of wire mode to be used, as shown in
Table 15-1.
Note:
Bit
0x0D
Read/Write
Initial Value
USIWM1
0
0
1
1
1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively
to avoid confusion between the modes of operation.
USIWM0
USISIE
Relationship between USIWM[1:0] and USI Operation
R/W
0
1
0
1
7
0
Description
Outputs, clock hold, and start detector disabled.
Port pins operates as normal.
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORTB register.
However, the corresponding DDRB bit still controls the data direction. When the port pin is
set as input the pin pull-up is controlled by the PORTB bit.
The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port operation.
When operating as master, clock pulses are software generated by toggling the PORTB
register, while the data direction is set to output. The USITC bit in the USICR Register can
be used for this purpose.
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and use open-
collector output drives. The output drivers are enabled by setting the corresponding bit for
SDA and SCL in the DDRB register.
When the output driver is enabled for the SDA pin it will force the line SDA low if the output
of the USI Data Register or the corresponding bit in the PORTB register is zero.
Otherwise, the SDA line will not be driven (i.e., it is released). When the SCL pin output
driver is enabled the SCL line will be forced low if the corresponding bit in the PORTB
register is zero, or by the start detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the output is
enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL
pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are
disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as in two-wire mode above, except that the SCL line is also held low
when a counter overflow occurs, and until the Counter Overflow Flag (USIOIF) is cleared.
USIOIE
R/W
6
0
USIWM1
R/W
5
0
USIWM0
R/W
4
0
page 119
page 119
USICS1
R/W
3
0
for further details.
Table 15-1
for further details.
USICS0
R/W
2
0
(1)
.
USICLK
below.
W
1
0
USITC
2586N–AVR–04/11
W
0
0
USICR