ATtiny85 Atmel Corporation, ATtiny85 Datasheet - Page 156

• Manufacturer Part Number: ATtiny85
• Manufacturer: Atmel Corporation

Specifications of ATtiny85

• Flash (kbytes): 8 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

20.5.1
156
ATtiny25/45/85
Serial Programming Algorithm
When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK.
When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See
Figure 21-4
To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in
1. Power-up sequence: apply power between V
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
set to “0”
– In some systems, the programmer can not guarantee that SCK is held low during
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program memory
Page is stored by loading the Write Program memory Page instruction with the 6 MSB
of the address. If polling (RDY/BSY) is not used, the user must wait at least t
before issuing the next page. (See
interface before the Flash write operation completes can result in incorrect
programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least t
In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the
Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by
loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM
Memory Page instruction is altered. The remaining locations remain unchanged. If poll-
ing (RDY/BSY) is not used, the used must wait at least t
next page (See
be programmed.
content at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
power-up. In this case, RESET must be given a positive pulse after SCK has been
set to '0'. The duration of the pulse must be at least t
See
and
CC
Table 21-4 on page 170
power off.
Figure 21-5
Table
20-9). In a chip erased device, no 0xFF in the data file(s) need to
for timing details.
WD_EEPROM
for minimum pulse width on RESET pin, t
Table
before issuing the next byte. (See
20-11.) Accessing the serial programming
CC
and GND while RESET and SCK are
RST
WD_EEPROM
Table
plus two CPU clock cycles.
20-12):
before issuing the
Table
RST
WD_FLASH
2586N–AVR–04/11
20-11.)