ATtiny85 Atmel Corporation, ATtiny85 Datasheet - Page 26

• Manufacturer Part Number: ATtiny85
• Manufacturer: Atmel Corporation

Specifications of ATtiny85

• Flash (kbytes): 8 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

6.2.1
6.2.2
26
ATtiny25/45/85
External Clock
High Frequency PLL Clock
mal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time.
The number of WDT Oscillator cycles used for each time-out is shown in
Table 6-2.
To drive the device from an external clock source, CLKI should be driven as shown in
4. To run the device on an external clock, the CKSEL Fuses must be programmed to “00”.
Figure 6-4.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table
Table 6-3.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to
31
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator
for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as
SUT[1:0]
for details.
00
01
10
11
6-3.
Typ Time-out
Number of Watchdog Oscillator Cycles
External Clock Drive Configuration
Start-up Times for the External Clock Selection
64 ms
Start-up Time from
4 ms
Power-down
6 CK
6 CK
6 CK
EXTERNAL
SIGNAL
CLOCK
Additional Delay from
Reserved
14CK + 64 ms
14CK + 4 ms
CLKI
GND
Reset
14CK
Number of Cycles
“System Clock Prescaler” on page
8K (8,192)
512
BOD enabled
Fast rising power
Slowly rising power
Recommended Usage
Table
6-2.
2586N–AVR–04/11
Figure 6-